Hardware/Latte IRQ controller

	Latte IRQ controller
Access
Espresso	Partial
Starbuck	Full
Registers
Base	0x0d800030, 0x0d800440
Length	0x14, 0x48
Access size	32 bits
Byte order	Big Endian
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The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both. IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LT).

IRQ Sources

IRQ	Group	Description
0	ALL	Timer (Starbuck)
1	ALL	NAND Interface
2	ALL	AES Engine
3	ALL	SHA-1 Engine
4	ALL	USB Host Controller (EHCI-0)
5	ALL	USB Host Controller (OHCI-0:0)
6	ALL	USB Host Controller (OHCI-0:1)
7	ALL	SD Host Controller
8	ALL	802.11 Wireless
9	ALL	Undefined
10	ALL	Latte GPIOs (Espresso)
11	ALL	Latte GPIOs (Starbuck)
12	ALL	SYSPROT
13	ALL	Undefined
14	ALL	Undefined
15	ALL	Undefined
16	ALL	USB Host Controller (EHCI-1)
17	ALL	Power button
18	ALL	Drive Interface
19	ALL	Undefined
20	ALL	EXI RTC
21	ALL	Undefined
22	ALL	Undefined
23	ALL	Undefined
24	ALL	Undefined
25	ALL	Undefined
26	ALL	Undefined
27	ALL	Undefined
28	ALL	SATA Controller (DBGINT only?)
29	ALL	Undefined
30	ALL	IPC (Espresso compat)
31	ALL	IPC (Starbuck compat)
0	LT	SD Host Controller (MMC)
1	LT	SD Host Controller (Unknown)
2	LT	Unknown
3	LT	USB Host Controller (OHCI-1:0)
4	LT	USB Host Controller (EHCI-2)
5	LT	USB Host Controller (OHCI-2:0)
6	LT	SATA Controller
7	LT	Unknown
8	LT	AES Engine (AESS)
9	LT	SHA-1 Engine (SHAS-1)
10	LT	Unknown
11	LT	Unknown
12	LT	Unknown
13	LT	I2C (Espresso)
14	LT	I2C (Starbuck)
15	LT	Undefined
16	LT	Undefined
17	LT	Undefined
18	LT	Undefined
19	LT	Undefined
20	LT	Undefined
21	LT	Undefined
22	LT	Undefined
23	LT	Undefined
24	LT	Undefined
25	LT	Undefined
26	LT	IPC (Espresso CPU2)
27	LT	IPC (Starbuck CPU2)
28	LT	IPC (Espresso CPU1)
29	LT	IPC (Starbuck CPU1)
30	LT	IPC (Espresso CPU0)
31	LT	IPC (Starbuck CPU0)

Register List

Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware. The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.

Wood block

Wood block
Address	Bits	Name	Description
0x0d800030	32	HW_PPCIRQFLAG	Triggered IRQs for the PPC core in vWii
0x0d800034	32	HW_PPCIRQMASK	Allowed IRQs for the PPC core in vWii
0x0d800038	32	HW_ARMIRQFLAG	Triggered IRQs for the ARM core in vWii
0x0d80003c	32	HW_ARMIRQMASK	Allowed IRQs for the ARM core in vWii
0x0d800040	32	HW_ARMFIQMASK	Allowed FIQs for the ARM core in vWii

Latte block

Latte block - PPC core 0
Address	Bits	Name	Description
0x0d800440	32	LT_PPCIRQFLAGALL0	Triggered IRQs for PPC core 0 (all)
0x0d800444	32	LT_PPCIRQFLAGLT0	Triggered IRQs for PPC core 0 (Latte only)
0x0d800448	32	LT_PPCIRQMASKALL0	Allowed IRQs for PPC core 0 (all)
0x0d80044c	32	LT_PPCIRQMASKLT0	Allowed IRQs for PPC core 0 (Latte only)

Latte block - PPC core 1
Address	Bits	Name	Description
0x0d800450	32	LT_PPCIRQFLAGALL1	Triggered IRQs for PPC core 1 (all)
0x0d800454	32	LT_PPCIRQFLAGLT1	Triggered IRQs for PPC core 1 (Latte only)
0x0d800458	32	LT_PPCIRQMASKALL1	Allowed IRQs for PPC core 1 (all)
0x0d80045c	32	LT_PPCIRQMASKLT1	Allowed IRQs for PPC core 1 (Latte only)

Latte block - PPC core 2
Address	Bits	Name	Description
0x0d800460	32	LT_PPCIRQFLAGALL2	Triggered IRQs for PPC core 2 (all)
0x0d800464	32	LT_PPCIRQFLAGLT2	Triggered IRQs for PPC core 2 (Latte only)
0x0d800468	32	LT_PPCIRQMASKALL2	Allowed IRQs for PPC core 2 (all)
0x0d80046c	32	LT_PPCIRQMASKLT2	Allowed IRQs for PPC core 2 (Latte only)

Latte block - ARM core
Address	Bits	Name	Description
0x0d800470	32	LT_ARMIRQFLAGALL	Triggered IRQs for ARM core (all)
0x0d800474	32	LT_ARMIRQFLAGLT	Triggered IRQs for ARM core (Latte only)
0x0d800478	32	LT_ARMIRQMASKALL	Allowed IRQs for ARM core (all)
0x0d80047c	32	LT_ARMIRQMASKLT	Allowed IRQs for ARM core (Latte only)
0x0d800480	32	LT_ARMFIQMASKALL	Allowed FIQs for the ARM core (all)
0x0d800484	32	LT_ARMFIQMASKLT	Allowed FIQs for the ARM core (Latte only)

Register descriptions

LT_PPCIRQFLAGALLx (0x0d800440/0x0d800450/0x0d800460)
	310
Access	R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.

LT_PPCIRQFLAGLTx (0x0d800444/0x0d800454/0x0d800464)
	310
Access	R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.

LT_PPCIRQMASKALLx (0x0d800448/0x0d800458/0x0d800468)
	310
Access	R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.

LT_PPCIRQMASKLTx (0x0d80044c/0x0d80045c/0x0d80046c)
	310
Access	R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.

LT_ARMIRQFLAGALL (0x0d800470)
	310
Access	R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.

LT_ARMIRQFLAGLT (0x0d800474)
	310
Access	R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.

LT_ARMIRQMASKALL (0x0d800478)
	310
Access	R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.

LT_ARMIRQMASKLT (0x0d80047c)
	310
Access	R/W