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→Register Details
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Line 88:
<br>+<br>+
== Register Details ==
== Register Details ==
+{{regsimple | EXIx_CR | addr = 0x0d80680c/0x0d806820/0x0d806834 | bits = 32 | access = W }}
+{{regsimple | EXIx_DATA | addr = 0x0d806810/0x0d806824/0x0d806838 | bits = 32 | access = R/W }}
+When IOSU sends data to the device, it:
+* Writes the data into EXI_DATA
+* Writes 0x35 into EXI_CR
+* Waits for [[Hardware/Latte_IRQ_Controller|IRQ]] #20
−When IOSU reads data from the device, it:
−* Writes 0x31 into EXI_CR
+* Waits for [[Hardware/Latte_IRQ_Controller|IRQ]] #20
+* Reads the data from EXI_DATA
= Audio Interface =
= Audio Interface =