In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/Processor interface"

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m (Hallowizer2 moved page Hardware/Processor Interface to Hardware/Processor interface: sentence case)
Line 6: Line 6:
 
}}
 
}}
  
−
==IRQ Sources==
+
== IRQ Sources ==
 
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 
|- style="background-color: #ddd;"
 
|- style="background-color: #ddd;"
−
! IRQ
+
! Bit
 +
! Group
 
! Description
 
! Description
−
! Connection
 
−
! Mask
 
 
|-
 
|-
−
|0 || Error || Processor Interface || 0x1
+
| 0 || ALL || ERROR
 
|-
 
|-
−
|1 || {{hw|DSP}} || Processor Interface || 0x40
+
| 1 || ALL || RSW
 
|-
 
|-
−
|2 || {{hw|GX2}} || Processor Interface (Latte) || 0x800000
+
| 2 || ALL || DI
 
|-
 
|-
−
|3 || GPIPPC (?) || AHB || 0x400
+
| 3 || ALL || SI
 
|-
 
|-
−
|4 || {{hw|I2C}} || AHB (Latte) || 0x2000
+
| 4 || ALL || Reserved
 
|-
 
|-
−
|5 || {{hw|Audio Interface}} (TV) || {{hw|DSP}} || 0x8
+
| 5 || ALL || AI
 
|-
 
|-
−
|6 || {{hw|Audio Interface}} (Gamepad) || {{hw|DSP}} (Latte) || 0x1000
+
| 6 || ALL || DSP
 
|-
 
|-
−
|7 || DSP Accelerator || {{hw|DSP}} || 0x20
+
| 7 || ALL || MEM
 
|-
 
|-
−
|8 || DSP DMA || {{hw|DSP}} || 0x80
+
| 8 || ALL || Reserved
 
|-
 
|-
−
|9 || {{hw|IPC}} (CPU0) || AHB (Latte) || 0x40000000
+
| 9 || ALL || Reserved
 
|-
 
|-
−
|10 || {{hw|IPC}} (CPU1) || AHB (Latte) || 0x10000000
+
| 10 || ALL || Reserved
 
|-
 
|-
−
|11 || {{hw|IPC}} (CPU2) || AHB (Latte) || 0x4000000
+
| 11 || ALL || Reserved
 
|-
 
|-
−
|12 || {{hw|Latte IRQ Controller}} || Processor Interface (Latte) || 0x1000000
+
| 12 || ALL || DEBUG
 +
|-
 +
| 13 || ALL || Reserved
 +
|-
 +
| 14 || ALL || Reserved
 +
|-
 +
| 15 || ALL || Reserved
 +
|-
 +
| 16 || LATTE || Reserved
 +
|-
 +
| 17 || LATTE || WG0_THRESHOLD
 +
|-
 +
| 18 || LATTE || WG1_THRESHOLD
 +
|-
 +
| 19 || LATTE || WG2_THRESHOLD
 +
|-
 +
| 20 || LATTE || MB_CPU0
 +
|-
 +
| 21 || LATTE || MB_CPU1
 +
|-
 +
| 22 || LATTE || MB_CPU2
 +
|-
 +
| 23 || LATTE || GPU7
 +
|-
 +
| 24 || LATTE || AHB
 +
|-
 +
| 25 || LATTE || Reserved
 +
|-
 +
| 26 || LATTE || Reserved
 +
|-
 +
| 27 || LATTE || Reserved
 +
|-
 +
| 28 || LATTE || Reserved
 +
|-
 +
| 29 || LATTE || Reserved
 +
|-
 +
| 30 || LATTE || Reserved
 +
|-
 +
| 31 || LATTE || Reserved
 
|}
 
|}
  

Revision as of 22:54, 17 May 2023

Processor interface
Access
EspressoFull
StarbuckNone
Registers
Base0x0c000000
Length0xc0000
Access size32 bits
Byte orderBig Endian
This box: view • talk • edit


IRQ Sources

Bit Group Description
0 ALL ERROR
1 ALL RSW
2 ALL DI
3 ALL SI
4 ALL Reserved
5 ALL AI
6 ALL DSP
7 ALL MEM
8 ALL Reserved
9 ALL Reserved
10 ALL Reserved
11 ALL Reserved
12 ALL DEBUG
13 ALL Reserved
14 ALL Reserved
15 ALL Reserved
16 LATTE Reserved
17 LATTE WG0_THRESHOLD
18 LATTE WG1_THRESHOLD
19 LATTE WG2_THRESHOLD
20 LATTE MB_CPU0
21 LATTE MB_CPU1
22 LATTE MB_CPU2
23 LATTE GPU7
24 LATTE AHB
25 LATTE Reserved
26 LATTE Reserved
27 LATTE Reserved
28 LATTE Reserved
29 LATTE Reserved
30 LATTE Reserved
31 LATTE Reserved

Register List

Processor Interface
Address Bits Name Description
0x0c000000 32 PI_INTSR_GLOBAL Globally-triggered IRQs
0x0c000004 32 PI_INTMR_GLOBAL Globally-allowed IRQs
0x0c000078 32 PI_INTSR_CPU0 Triggered IRQs for CPU0
0x0c00007c 32 PI_INTMR_CPU0 Allowed IRQs for CPU0
0x0c000080 32 PI_INTSR_CPU1 Triggered IRQs for CPU1
0x0c000084 32 PI_INTMR_CPU1 Allowed IRQs for CPU1
0x0c000088 32 PI_INTSR_CPU2 Triggered IRQs for CPU2
0x0c00008c 32 PI_INTMR_CPU2 Allowed IRQs for CPU2

Register Details

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