Changes

Note that, since the interrupts can actually route to either or both the Starbuck and Espresso, and since the Starbuck can also access the Espresso's registers, there are ways of abusing these flags for odd purposes.

Note that, since the interrupts can actually route to either or both the Starbuck and Espresso, and since the Starbuck can also access the Espresso's registers, there are ways of abusing these flags for odd purposes.

Registers HW_IPC_ARMCTRL and LT_IPC_ARMCTRLx can only be accessed by the Starbuck. The others can be accessed by both CPUs.

Registers HW_IPCIOPCTRL and LT_IPCIOPCTRLx can only be accessed by the Starbuck. The others can be accessed by both CPUs.

== Register List ==

== Register List ==

=== Wood block ===

=== Wood block ===

{{reglist|Wood block}}

{{reglist|Wood block}}

{{rla|0x0d800000|32|HW_IPC_PPCMSG|Espresso data register for vWii}}

{{rla|0x0d800000|32|HW_IPCPPCMSG|Espresso data register for vWii}}

{{rla|0x0d800004|32|HW_IPC_PPCCTRL|Espresso flags and control for vWii}}

{{rla|0x0d800004|32|HW_IPCPPCCTRL|Espresso flags and control for vWii}}

{{rla|0x0d800008|32|HW_IPC_ARMMSG|Starbuck data register for vWii}}

{{rla|0x0d800008|32|HW_IPCIOPMSG|Starbuck data register for vWii}}

{{rla|0x0d80000c|32|HW_IPC_ARMCTRL|Starbuck flags and control for vWii}}

{{rla|0x0d80000c|32|HW_IPCIOPCTRL|Starbuck flags and control for vWii}}

|}

|}

=== Latte block ===

=== Latte block ===

{{reglist|Latte block - PPC core 0}}

{{reglist|Latte block - PPC core 0}}

{{rla|0x0d800400|32|LT_IPC_PPCMSG0|Espresso data register for PPC core 0}}

{{rla|0x0d800400|32|LT_IPCPPCMSG0|Espresso data register for PPC core 0}}

{{rla|0x0d800404|32|LT_IPC_PPCCTRL0|Espresso flags and control for PPC core 0}}

{{rla|0x0d800404|32|LT_IPCPPCCTRL0|Espresso flags and control for PPC core 0}}

{{rla|0x0d800408|32|LT_IPC_ARMMSG0|Starbuck data register for PPC core 0}}

{{rla|0x0d800408|32|LT_IPCIOPMSG0|Starbuck data register for PPC core 0}}

{{rla|0x0d80040c|32|LT_IPC_ARMCTRL0|Starbuck flags and control for PPC core 0}}

{{rla|0x0d80040c|32|LT_IPCIOPCTRL0|Starbuck flags and control for PPC core 0}}

|}

|}

{{reglist|Latte block - PPC core 1}}

{{reglist|Latte block - PPC core 1}}

{{rla|0x0d800410|32|LT_IPC_PPCMSG1|Espresso data register for PPC core 1}}

{{rla|0x0d800410|32|LT_IPCPPCMSG1|Espresso data register for PPC core 1}}

{{rla|0x0d800414|32|LT_IPC_PPCCTRL1|Espresso flags and control for PPC core 1}}

{{rla|0x0d800414|32|LT_IPCPPCCTRL1|Espresso flags and control for PPC core 1}}

{{rla|0x0d800418|32|LT_IPC_ARMMSG1|Starbuck data register for PPC core 1}}

{{rla|0x0d800418|32|LT_IPCIOPMSG1|Starbuck data register for PPC core 1}}

{{rla|0x0d80041c|32|LT_IPC_ARMCTRL1|Starbuck flags and control for PPC core 1}}

{{rla|0x0d80041c|32|LT_IPCIOPCTRL1|Starbuck flags and control for PPC core 1}}

|}

|}

{{reglist|Latte block - PPC core 2}}

{{reglist|Latte block - PPC core 2}}

{{rla|0x0d800420|32|LT_IPC_PPCMSG2|Espresso data register for PPC core 2}}

{{rla|0x0d800420|32|LT_IPCPPCMSG2|Espresso data register for PPC core 2}}

{{rla|0x0d800424|32|LT_IPC_PPCCTRL2|Espresso flags and control for PPC core 2}}

{{rla|0x0d800424|32|LT_IPCPPCCTRL2|Espresso flags and control for PPC core 2}}

{{rla|0x0d800428|32|LT_IPC_ARMMSG2|Starbuck data register for PPC core 2}}

{{rla|0x0d800428|32|LT_IPCIOPMSG2|Starbuck data register for PPC core 2}}

{{rla|0x0d80042c|32|LT_IPC_ARMCTRL2|Starbuck flags and control for PPC core 2}}

{{rla|0x0d80042c|32|LT_IPCIOPCTRL2|Starbuck flags and control for PPC core 2}}

|}

|}

== Register Details ==

== Register Details ==

{{regsimple | LT_IPC_PPCMSGx | addr = 0x0d800400/0x0d800410/0x0d800420 | bits = 32 | access = R/W }}

{{regsimple | LT_IPCPPCMSGx | addr = 0x0d800400/0x0d800410/0x0d800420 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

----

----

{{reg32 | LT_IPC_PPCCTRLx | addr = 0x0d800404/0x0d800414/0x0d800424 | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPCPPCCTRLx | addr = 0x0d800404/0x0d800414/0x0d800424 | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|

=== IOS usage ===

=== IOS usage ===

{{regdesc

{{regdesc

|X1|Execute command: a new pointer is available in ''LT_IPC_PPCCTRLx''

|X1|Execute command: a new pointer is available in ''LT_IPCPPCCTRLx''

|Y2|Command acknowledge

|Y2|Command acknowledge

|Y1|Command executed and reply available in ''LT_IPC_ARMMSGx''

|Y1|Command executed and reply available in ''LT_IPCIOPMSGx''

|X2|Relaunch

|X2|Relaunch

}}

}}

----

----

{{regsimple | LT_IPC_ARMMSGx | addr = 0x0d800408/0x0d800418/0x0d800428 | bits = 32 | access = R/W }}

{{regsimple | LT_IPCIOPMSGx | addr = 0x0d800408/0x0d800418/0x0d800428 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

----

----

{{reg32 | LT_IPC_ARMCTRLx | addr = 0x0d80040c/0x0d80041c/0x0d80042c | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPCIOPCTRLx | addr = 0x0d80040c/0x0d80041c/0x0d80042c | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|