Changes

364 bytes added ,  03:01, 27 November 2023
no edit summary
Line 57: Line 57:  
| 0x400000
 
| 0x400000
 
| MMIO
 
| MMIO
| [[:Cafe_OS|Espresso registers]] (GX2/DSP/OTP)
+
| {{hw|Espresso Registers}} (GX2/DSP/OTP)
 
|-
 
|-
 
| 0x0D000000
 
| 0x0D000000
| ??????
+
| 0x0D005FFF
| ??????
+
| 0x6000
 
| MMIO
 
| MMIO
| [[:Hardware/Latte_Registers|Latte registers (shared with Espresso)]]
+
| [[:Hardware/Latte_registers|Latte registers (shared with Espresso)]]
 
|-
 
|-
 
| 0x0D006000
 
| 0x0D006000
| 0x0D006FFF
+
| 0x0D00FFFF
| 0x1000
+
| 0xA000
 
| MMIO
 
| MMIO
 
| [[:Hardware/Legacy|Legacy registers]] (DI/SI/EXI/AI)
 
| [[:Hardware/Legacy|Legacy registers]] (DI/SI/EXI/AI)
Line 75: Line 75:  
| 0x10000
 
| 0x10000
 
| MMIO
 
| MMIO
| [[:Hardware/NAND_Interface|NAND registers]]
+
| [[:Hardware/NAND_interface|NAND registers]]
 +
|-
 +
| 0x0D020000
 +
| 0x0D02FFFF
 +
| 0x10000
 +
| MMIO
 +
| [[:Hardware/AES_engine|AES registers]] (has a virtual mapping at 0x0D820000)
 +
|-
 +
| 0x0D030000
 +
| 0x0D03FFFF
 +
| 0x10000
 +
| MMIO
 +
| [[:Hardware/SHA-1_engine|SHA-1 registers]] (has a virtual mapping at 0x0D830000)
 
|-
 
|-
 
| 0x0D040000
 
| 0x0D040000
Line 99: Line 111:  
| 0x10000
 
| 0x10000
 
| MMIO
 
| MMIO
| [[:Hardware/SD_Host_Controller|SD Host registers]]
+
| [[:Hardware/SD_Host_Controller|SDIO registers]]
 
|-
 
|-
 
| 0x0D080000
 
| 0x0D080000
Line 105: Line 117:  
| 0x10000
 
| 0x10000
 
| MMIO
 
| MMIO
| [[:Hardware/802.11_Wireless|802.11 Wireless registers]]
+
| [[:Hardware/SD_Host_Controller|SDIO registers]] ([[:Hardware/802.11_Wireless|802.11 Wireless]])
 
|-
 
|-
 
| 0x0D100000
 
| 0x0D100000
Line 111: Line 123:  
| 0x10000
 
| 0x10000
 
| MMIO
 
| MMIO
| Unknown (mapped for IOS-FS)
+
| [[:Hardware/SD_Host_Controller|SDIO registers]] (eMMC)
 
|-
 
|-
 
| 0x0D110000
 
| 0x0D110000
Line 117: Line 129:  
| 0x10000
 
| 0x10000
 
| MMIO
 
| MMIO
| Unknown (mapped for IOS-FS)
+
| [[:Hardware/SD_Host_Controller|SDIO registers]] (Toucan)
 
|-
 
|-
 
| 0x0D120000
 
| 0x0D120000
Line 148: Line 160:  
| MMIO
 
| MMIO
 
| [[:Hardware/SATA_Controller|SATA registers]]
 
| [[:Hardware/SATA_Controller|SATA registers]]
 +
|-
 +
| 0x0D180000
 +
| 0x0D18FFFF
 +
| 0x10000
 +
| MMIO
 +
| [[:Hardware/AES_engine|AESS registers]] (has a virtual mapping at 0x0D980000)
 +
|-
 +
| 0x0D190000
 +
| 0x0D19FFFF
 +
| 0x10000
 +
| MMIO
 +
| [[:Hardware/SHA-1_engine|SHAS-1 registers]] (has a virtual mapping at 0x0D990000)
 
|-
 
|-
 
| 0x0D400000
 
| 0x0D400000
Line 153: Line 177:  
| 0x10000
 
| 0x10000
 
| SRAM1
 
| SRAM1
| BOOT1 (mirrored in 0xFFF00000)
+
| [[boot1]] (mirrored in 0xFFF00000)
 
|-
 
|-
 
| 0x0D410000
 
| 0x0D410000
Line 159: Line 183:  
| 0x10000
 
| 0x10000
 
| SRAM0
 
| SRAM0
| BOOT0 (mirrored in 0xFFFF0000)
+
| [[:boot0]] (mirrored in 0xFFFF0000)
 
|-
 
|-
 
| 0x0D800000
 
| 0x0D800000
| ??????
+
| 0x0D805FFF
| ??????
+
| 0x6000
 
| MMIO
 
| MMIO
| [[:Hardware/Latte_Registers|Latte registers]]
+
| [[:Hardware/Latte_registers|Latte registers]]
 
|-
 
|-
| 0x0D820000
+
| 0x0D8B0000
| 0x0D82FFFF
+
| 0x0D8B3FFF
| 0x10000
+
| 0x4000
 
| MMIO
 
| MMIO
| [[:Hardware/AES_Engine|AES registers]] (has a virtual mapping at 0x0D020000)
+
| [[:Hardware/AHMN_controller|AHMN registers]]
|-
  −
| 0x0D830000
  −
| 0x0D83FFFF
  −
| 0x10000
  −
| MMIO
  −
| [[:Hardware/SHA-1_Engine|SHA-1 registers]] (has a virtual mapping at 0x0D030000)
  −
|-
  −
| 0x0D8B0800
  −
| ??????
  −
| ??????
  −
| MMIO
  −
| [[:Hardware/XN_Controller|AHMN registers]]
   
|-
 
|-
 
| 0x0D8B4000
 
| 0x0D8B4000
| ??????
+
| 0x0D8BFFFF
| ??????
+
| 0xC000
 
| MMIO
 
| MMIO
| [[:Hardware/Memory_Controller|Memory Controller registers]]
+
| [[:Hardware/Memory_controller|Memory Controller registers]]
|-
  −
| 0x0D980000
  −
| 0x0D98FFFF
  −
| 0x10000
  −
| MMIO
  −
| [[:Hardware/AES_Engine|AESS registers]] (has a virtual mapping at 0x0D180000)
  −
|-
  −
| 0x0D990000
  −
| 0x0D99FFFF
  −
| 0x10000
  −
| MMIO
  −
| [[:Hardware/SHA-1_Engine|SHAS-1 registers]] (has a virtual mapping at 0x0D190000)
   
|-
 
|-
 
| 0x10000000
 
| 0x10000000
Line 207: Line 207:  
| 0x100000
 
| 0x100000
 
| MEM2
 
| MEM2
| Unknown (IOSU)
+
| [[Boot1#get_boot_info|boot1 warmboot PRSH/PRST]]
 
|-
 
|-
 
| 0x10100000
 
| 0x10100000
Line 319: Line 319:  
| 0x8000000
 
| 0x8000000
 
| MEM2
 
| MEM2
| Unknown (IOSU)
+
| RAMDISK
 
|-
 
|-
 
| 0x28000000
 
| 0x28000000
Line 348: Line 348:  
| SRAM1
 
| SRAM1
 
| C2W (cafe2wii) boot heap (used to store the old Wii SEEPROM data)
 
| C2W (cafe2wii) boot heap (used to store the old Wii SEEPROM data)
 +
|-
 +
| 0xFFFE0000
 +
| 0xFFFE7FFF
 +
| 0x8000
 +
| SRAM1
 +
| Mirror of SRAM1. Hai C2W uses this one for (some) Hai params instead of the former?<br>IOS80 also uses this one for SEEPROM data despite the data being written to the former.
 
|-
 
|-
 
| 0xFFFF0000
 
| 0xFFFF0000