In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/Processor interface"

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(→‎IRQ Sources: Add connections to IRQs)
 
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}}
 
}}
  
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==IRQ Sources==
+
== IRQ Sources ==
−
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
+
{| class="wikitable"
−
|- style="background-color: #ddd;"
+
|-
−
! IRQ
+
! Bit
 +
! Group
 
! Description
 
! Description
−
! Connection
 
 
|-
 
|-
−
|0 || Error || Processor Interface
+
| 0 || ALL || ERROR
 +
|-
 +
| 1 || ALL || RSW
 +
|-
 +
| 2 || ALL || DI
 +
|-
 +
| 3 || ALL || SI
 +
|-
 +
| 4 || ALL || Reserved
 +
|-
 +
| 5 || ALL || AI
 +
|-
 +
| 6 || ALL || DSP
 +
|-
 +
| 7 || ALL || MEM
 +
|-
 +
| 8 || ALL || Reserved
 +
|-
 +
| 9 || ALL || Reserved
 +
|-
 +
| 10 || ALL || Reserved
 +
|-
 +
| 11 || ALL || Reserved
 +
|-
 +
| 12 || ALL || DEBUG
 +
|-
 +
| 13 || ALL || Reserved
 +
|-
 +
| 14 || ALL || Reserved
 +
|-
 +
| 15 || ALL || Reserved
 +
|-
 +
| 16 || LATTE || Reserved
 +
|-
 +
| 17 || LATTE || WG0_THRESHOLD
 +
|-
 +
| 18 || LATTE || WG1_THRESHOLD
 +
|-
 +
| 19 || LATTE || WG2_THRESHOLD
 
|-
 
|-
−
|1 || {{hw|DSP}} (all DSP IRQs) || Processor Interface
+
| 20 || LATTE || MB_CPU0
 
|-
 
|-
−
|2 || {{hw|GX2}} || Processor Interface (Latte)
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| 21 || LATTE || MB_CPU1
 
|-
 
|-
−
|3 || GPIPPC (?) || AHB
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| 22 || LATTE || MB_CPU2
 
|-
 
|-
−
|4 || {{hw|I2C}} || AHB (Latte)
+
| 23 || LATTE || GPU7
 
|-
 
|-
−
|5 || {{hw|Audio Interface}} (TV) || {{hw|DSP}}
+
| 24 || LATTE || AHB
 
|-
 
|-
−
|6 || {{hw|Audio Interface}} (Gamepad) || {{hw|DSP}} (Latte)
+
| 25 || LATTE || Reserved
 
|-
 
|-
−
|7 || ACC (?) || {{hw|DSP}}
+
| 26 || LATTE || Reserved
 
|-
 
|-
−
|8 || {{hw|DSP}} (again?) || {{hw|DSP}}
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| 27 || LATTE || Reserved
 
|-
 
|-
−
|9 || {{hw|IPC}} (CPU0) || AHB (Latte)
+
| 28 || LATTE || Reserved
 
|-
 
|-
−
|10 || {{hw|IPC}} (CPU1) || AHB (Latte)
+
| 29 || LATTE || Reserved
 
|-
 
|-
−
|11 || {{hw|IPC}} (CPU2) || AHB (Latte)
+
| 30 || LATTE || Reserved
 
|-
 
|-
−
|12 || {{hw|Latte IRQs}} || Processor Interface (Latte)
+
| 31 || LATTE || Reserved
 
|}
 
|}
  
−
==Register List==
+
== Register List ==
 
{{reglist|Processor Interface}}
 
{{reglist|Processor Interface}}
−
{{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}}
+
{{rla|0x0c000000|32|PI_INTSTS|Triggered IRQs}}
−
{{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}}
+
{{rla|0x0c000004|32|PI_INTEN|Allowed IRQs}}
−
{{rla|0x0c000078|32|PI_INTSR_CPU0|Triggered IRQs for CPU0}}
+
{{rla|0x0c000040|32|PI_WG0UNK0|Write Gather Pipe related}}
−
{{rla|0x0c00007c|32|PI_INTMR_CPU0|Allowed IRQs for CPU0}}
+
{{rla|0x0c000044|32|PI_WG0UNK1|Write Gather Pipe related}}
−
{{rla|0x0c000080|32|PI_INTSR_CPU1|Triggered IRQs for CPU1}}
+
{{rla|0x0c000048|32|PI_WG0UNK2|Write Gather Pipe related}}
−
{{rla|0x0c000084|32|PI_INTMR_CPU1|Allowed IRQs for CPU1}}
+
{{rla|0x0c00004c|32|PI_WG0UNK3|Write Gather Pipe related}}
−
{{rla|0x0c000088|32|PI_INTSR_CPU2|Triggered IRQs for CPU2}}
+
{{rla|0x0c000050|32|PI_WG1UNK0|Write Gather Pipe related}}
−
{{rla|0x0c00008c|32|PI_INTMR_CPU2|Allowed IRQs for CPU2}}
+
{{rla|0x0c000054|32|PI_WG1UNK1|Write Gather Pipe related}}
 +
{{rla|0x0c000058|32|PI_WG1UNK2|Write Gather Pipe related}}
 +
{{rla|0x0c00005c|32|PI_WG1UNK3|Write Gather Pipe related}}
 +
{{rla|0x0c000060|32|PI_WG2UNK0|Write Gather Pipe related}}
 +
{{rla|0x0c000064|32|PI_WG2UNK1|Write Gather Pipe related}}
 +
{{rla|0x0c000068|32|PI_WG2UNK2|Write Gather Pipe related}}
 +
{{rla|0x0c00006c|32|PI_WG2UNK3|Write Gather Pipe related}}
 +
{{rla|0x0c000078|32|PI_CPU0INTSTS|Triggered IRQs for CPU 0}}
 +
{{rla|0x0c00007c|32|PI_CPU0INTEN|Allowed IRQs for CPU 0}}
 +
{{rla|0x0c000080|32|PI_CPU1INTSTS|Triggered IRQs for CPU 1}}
 +
{{rla|0x0c000084|32|PI_CPU1INTEN|Allowed IRQs for CPU 1}}
 +
{{rla|0x0c000088|32|PI_CPU2INTSTS|Triggered IRQs for CPU 2}}
 +
{{rla|0x0c00008c|32|PI_CPU2INTEN|Allowed IRQs for CPU 2}}
 
|}
 
|}
  
−
==Register Details==
+
== Register Details ==

Latest revision as of 03:17, 19 February 2024

Processor interface
Access
EspressoFull
StarbuckNone
Registers
Base0x0c000000
Length0xc0000
Access size32 bits
Byte orderBig Endian
This box: view • talk • edit


IRQ Sources

Bit Group Description
0 ALL ERROR
1 ALL RSW
2 ALL DI
3 ALL SI
4 ALL Reserved
5 ALL AI
6 ALL DSP
7 ALL MEM
8 ALL Reserved
9 ALL Reserved
10 ALL Reserved
11 ALL Reserved
12 ALL DEBUG
13 ALL Reserved
14 ALL Reserved
15 ALL Reserved
16 LATTE Reserved
17 LATTE WG0_THRESHOLD
18 LATTE WG1_THRESHOLD
19 LATTE WG2_THRESHOLD
20 LATTE MB_CPU0
21 LATTE MB_CPU1
22 LATTE MB_CPU2
23 LATTE GPU7
24 LATTE AHB
25 LATTE Reserved
26 LATTE Reserved
27 LATTE Reserved
28 LATTE Reserved
29 LATTE Reserved
30 LATTE Reserved
31 LATTE Reserved

Register List

Processor Interface
Address Bits Name Description
0x0c000000 32 PI_INTSTS Triggered IRQs
0x0c000004 32 PI_INTEN Allowed IRQs
0x0c000040 32 PI_WG0UNK0 Write Gather Pipe related
0x0c000044 32 PI_WG0UNK1 Write Gather Pipe related
0x0c000048 32 PI_WG0UNK2 Write Gather Pipe related
0x0c00004c 32 PI_WG0UNK3 Write Gather Pipe related
0x0c000050 32 PI_WG1UNK0 Write Gather Pipe related
0x0c000054 32 PI_WG1UNK1 Write Gather Pipe related
0x0c000058 32 PI_WG1UNK2 Write Gather Pipe related
0x0c00005c 32 PI_WG1UNK3 Write Gather Pipe related
0x0c000060 32 PI_WG2UNK0 Write Gather Pipe related
0x0c000064 32 PI_WG2UNK1 Write Gather Pipe related
0x0c000068 32 PI_WG2UNK2 Write Gather Pipe related
0x0c00006c 32 PI_WG2UNK3 Write Gather Pipe related
0x0c000078 32 PI_CPU0INTSTS Triggered IRQs for CPU 0
0x0c00007c 32 PI_CPU0INTEN Allowed IRQs for CPU 0
0x0c000080 32 PI_CPU1INTSTS Triggered IRQs for CPU 1
0x0c000084 32 PI_CPU1INTEN Allowed IRQs for CPU 1
0x0c000088 32 PI_CPU2INTSTS Triggered IRQs for CPU 2
0x0c00008c 32 PI_CPU2INTEN Allowed IRQs for CPU 2

Register Details

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