WiiUBrew

Changes

Hardware/Espresso (view source)

Revision as of 21:55, 23 February 2024

4,862 bytes added ,  21:55, 23 February 2024
→‎HID5
Line 1: Line 1: −
Espresso is the code name for the Wii U's PowerPC processor.
+
'''Espresso''' is the code name for the Wii U's PowerPC processor. Unlike the [https://wiibrew.org/wiki/Broadway Broadway], the Espresso contains a secure [[Espresso Boot ROM|boot ROM]] so that if the [[Hardware/Starbuck|Starbuck]] is taken over, Espresso code execution should not be possible.
   −
== Special Purpose Registers ==
+
== MSR ==
−
Note: This section is redundant to [[SPRs]].
+
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0
 +
|LE
 +
|-
 +
|1
 +
|RI
 +
|-
 +
|2
 +
|PM
 +
|-
 +
|3
 +
|Reserved
 +
|-
 +
|4
 +
|DR
 +
|-
 +
|5
 +
|IR
 +
|-
 +
|6
 +
|IP
 +
|-
 +
|7
 +
|Reserved
 +
|-
 +
|8
 +
|FE1
 +
|-
 +
|9
 +
|BE
 +
|-
 +
|10
 +
|SE
 +
|-
 +
|11
 +
|FE0
 +
|-
 +
|12
 +
|ME
 +
|-
 +
|13
 +
|FP
 +
|-
 +
|14
 +
|PR
 +
|-
 +
|15
 +
|EE
 +
|-
 +
|16
 +
|ILE
 +
|-
 +
|17
 +
|Reserved
 +
|-
 +
|18
 +
|POW
 +
|-
 +
|19-31
 +
|Reserved
 +
|}
    +
== SPR ==
 
{| class="wikitable"
 
{| class="wikitable"
 
!|Index
 
!|Index
 
!|Name
 
!|Name
−
!|Description
   
|-
 
|-
−
|0x3b0
+
|0x1
−
|HID5[0]
+
|XER
−
|Enable HID5
+
|-
 +
|0x8
 +
|LR
 +
|-
 +
|0x9
 +
|CTR
 +
|-
 +
|0x12
 +
|DSISR
 +
|-
 +
|0x13
 +
|DAR
 +
|-
 +
|0x16
 +
|DEC
 +
|-
 +
|0x19
 +
|SDR1
 +
|-
 +
|0x1A
 +
|SRR0
 +
|-
 +
|0x1B
 +
|SRR1
 +
|-
 +
|0x10C
 +
|UTBL
 +
|-
 +
|0x10D
 +
|UTBU
 +
|-
 +
|0x110
 +
|SPRG0
 +
|-
 +
|0x111
 +
|SPRG1
 +
|-
 +
|0x112
 +
|SPRG2
 +
|-
 +
|0x113
 +
|SPRG3
 +
|-
 +
|0x11A
 +
|EAR
 +
|-
 +
|0x11C
 +
|TBL
 +
|-
 +
|0x11D
 +
|TBU
 +
|-
 +
|0x11F
 +
|PVR
 +
|-
 +
|0x210
 +
|IBAT0U
 +
|-
 +
|0x211
 +
|IBAT0L
 +
|-
 +
|0x212
 +
|IBAT1U
 +
|-
 +
|0x213
 +
|IBAT1L
 +
|-
 +
|0x214
 +
|IBAT2U
 +
|-
 +
|0x215
 +
|IBAT2L
 +
|-
 +
|0x216
 +
|IBAT3U
 +
|-
 +
|0x217
 +
|IBAT3L
 +
|-
 +
|0x218
 +
|DBAT0U
 +
|-
 +
|0x219
 +
|DBAT0L
 +
|-
 +
|0x21A
 +
|DBAT1U
 +
|-
 +
|0x21B
 +
|DBAT1L
 +
|-
 +
|0x21C
 +
|DBAT2U
 +
|-
 +
|0x21D
 +
|DBAT2L
 +
|-
 +
|0x21E
 +
|DBAT3U
 +
|-
 +
|0x21F
 +
|DBAT3L
 +
|-
 +
|0x230
 +
|IBAT4U
 +
|-
 +
|0x231
 +
|IBAT4L
 +
|-
 +
|0x232
 +
|IBAT5U
 +
|-
 +
|0x233
 +
|IBAT5L
 +
|-
 +
|0x234
 +
|IBAT6U
 +
|-
 +
|0x235
 +
|IBAT6L
 +
|-
 +
|0x236
 +
|IBAT7U
 +
|-
 +
|0x237
 +
|IBAT7L
 +
|-
 +
|0x238
 +
|DBAT4U
 +
|-
 +
|0x239
 +
|DBAT4L
 +
|-
 +
|0x23A
 +
|DBAT5U
 +
|-
 +
|0x23B
 +
|DBAT5L
 +
|-
 +
|0x23C
 +
|DBAT6U
 +
|-
 +
|0x23D
 +
|DBAT6L
 +
|-
 +
|0x23E
 +
|DBAT7U
 +
|-
 +
|0x23F
 +
|DBAT7L
 +
|-
 +
|0x380
 +
|UGQR0
 +
|-
 +
|0x381
 +
|UGQR1
 +
|-
 +
|0x382
 +
|UGQR2
 +
|-
 +
|0x383
 +
|UGQR3
 +
|-
 +
|0x384
 +
|UGQR4
 +
|-
 +
|0x385
 +
|UGQR5
 +
|-
 +
|0x386
 +
|UGQR6
 +
|-
 +
|0x387
 +
|UGQR7
 +
|-
 +
|0x388
 +
|UHID2
 +
|-
 +
|0x389
 +
|UWPAR
 +
|-
 +
|0x38A
 +
|UDMAU
 +
|-
 +
|0x38B
 +
|UDMAL
 +
|-
 +
|0x390
 +
|GQR0
 +
|-
 +
|0x391
 +
|GQR1
 +
|-
 +
|0x392
 +
|GQR2
 +
|-
 +
|0x393
 +
|GQR3
 +
|-
 +
|0x394
 +
|GQR4
 +
|-
 +
|0x395
 +
|GQR5
 +
|-
 +
|0x396
 +
|GQR6
 +
|-
 +
|0x397
 +
|GQR7
 +
|-
 +
|0x398
 +
|[[#HID2|HID2]]
 +
|-
 +
|0x399
 +
|WPAR
 +
|-
 +
|0x39A
 +
|[[#DMA_U|DMA_U]]
 +
|-
 +
|0x39B
 +
|[[#DMA_L|DMA_L]]
 +
|-
 +
|0x3A8
 +
|UMMCR0
 +
|-
 +
|0x3A9
 +
|UPMC1
 +
|-
 +
|0x3AA
 +
|UPMC2
 +
|-
 +
|0x3AB
 +
|USIA
 +
|-
 +
|0x3AC
 +
|UMMCR1
 +
|-
 +
|0x3AD
 +
|UPMC3
 +
|-
 +
|0x3AE
 +
|UPMC4
 +
|-
 +
|0x3B0
 +
|[[#HID5|HID5]]
 
|-
 
|-
−
|0x3b0
+
|0x3B2
−
|HID5[1]
+
|PCSR
−
|Enable PIR
   
|-
 
|-
 
|0x3B3
 
|0x3B3
−
|SCR[1]
+
|[[#SCR|SCR]]
−
|Enable bootrom (reset only)
+
|-
 +
|0x3B4
 +
|CAR
 +
|-
 +
|0x3B5
 +
|BCR
 +
|-
 +
|0x3B6
 +
|WPSAR
 +
|-
 +
|0x3B8
 +
|MMCR0
 +
|-
 +
|0x3B9
 +
|PMC1
 +
|-
 +
|0x3BA
 +
|PMC2
 +
|-
 +
|0x3BB
 +
|SIA
 +
|-
 +
|0x3BC
 +
|MMCR1
 +
|-
 +
|0x3BD
 +
|PMC3
 +
|-
 +
|0x3BE
 +
|PMC4
 +
|-
 +
|0x3D0
 +
|DCATE
 +
|-
 +
|0x3D1
 +
|DCATR
 +
|-
 +
|0x3D8
 +
|DMATL0
 
|-
 
|-
−
|0x3B3
+
|0x3D9
−
|SCR[2]
+
|DMATU0
−
|Enable keystore 00..1f (reset only)
+
|-
 +
|0x3DA
 +
|DMATR0
 
|-
 
|-
−
|0x3B3
+
|0x3DB
−
|SCR[3]
+
|DMATL1
−
|Enable keystore 20..3f (reset only)
   
|-
 
|-
−
|0x3B3
+
|0x3DC
−
|SCR[9]
+
|DMATU1
−
|Start core 1
   
|-
 
|-
−
|0x3B3
+
|0x3DD
−
|SCR[10]
+
|DMATR1
−
|Start core 2
   
|-
 
|-
 
|0x3EF
 
|0x3EF
 
|PIR
 
|PIR
−
|CPU core index (Processor Index Register)
+
|-
 +
|0x3F0
 +
|[[#HID0|HID0]]
 +
|-
 +
|0x3F1
 +
|[[#HID1|HID1]]
 +
|-
 +
|0x3F2
 +
|IABR
 +
|-
 +
|0x3F3
 +
|[[#HID4|HID4]]
 +
|-
 +
|0x3F4
 +
|TDCL
 +
|-
 +
|0x3F5
 +
|DABR
 +
|-
 +
|0x3F9
 +
|[[#L2CR|L2CR]]
 +
|-
 +
|0x3FA
 +
|TDCH
 +
|-
 +
|0x3FB
 +
|ICTC
 +
|-
 +
|0x3FC
 +
|THRM1
 +
|-
 +
|0x3FD
 +
|THRM2
 +
|-
 +
|0x3FE
 +
|THRM3
 +
|}
 +
 
 +
=== DMA_U ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-4
 +
|DMA_LEN_U
 +
|-
 +
|5-31
 +
|MEM_ADDR
 +
|}
 +
 
 +
=== DMA_L ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0
 +
|DMA_F
 +
|-
 +
|1
 +
|DMA_T
 +
|-
 +
|2-3
 +
|DMA_LEN_L
 +
|-
 +
|4
 +
|DMA_LD
 +
|-
 +
|5-31
 +
|LC_ADDR
 
|}
 
|}
 +
 +
=== L2CR ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0
 +
|L2IP
 +
|-
 +
|1-17
 +
|Reserved
 +
|-
 +
|18
 +
|L2TS
 +
|-
 +
|19
 +
|L2WT
 +
|-
 +
|20
 +
|Reserved
 +
|-
 +
|21
 +
|L2I
 +
|-
 +
|22
 +
|L2DO
 +
|-
 +
|23-29
 +
|Reserved
 +
|-
 +
|30
 +
|L2CE
 +
|-
 +
|31
 +
|L2E
 +
|}
 +
 +
=== HID0 ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0
 +
|NOOPTI
 +
|-
 +
|1
 +
|Reserved
 +
|-
 +
|2
 +
|BHT
 +
|-
 +
|3
 +
|ABE
 +
|-
 +
|4
 +
|Reserved
 +
|-
 +
|5
 +
|BTIC
 +
|-
 +
|6
 +
|DCFA
 +
|-
 +
|7
 +
|SGE
 +
|-
 +
|8
 +
|IFEM
 +
|-
 +
|9
 +
|SPD
 +
|-
 +
|10
 +
|DCFI
 +
|-
 +
|11
 +
|ICFI
 +
|-
 +
|12
 +
|DLOCK
 +
|-
 +
|13
 +
|ILOCK
 +
|-
 +
|14
 +
|DCE
 +
|-
 +
|15
 +
|ICE
 +
|-
 +
|16
 +
|NHR
 +
|-
 +
|17-19
 +
|Reserved
 +
|-
 +
|20
 +
|DPM
 +
|-
 +
|21
 +
|SLEEP
 +
|-
 +
|22
 +
|NAP
 +
|-
 +
|23
 +
|DOZE
 +
|-
 +
|24
 +
|PAR
 +
|-
 +
|25
 +
|ECLK
 +
|-
 +
|26
 +
|Reserved
 +
|-
 +
|27
 +
|BCLK
 +
|-
 +
|28
 +
|EBD
 +
|-
 +
|29
 +
|EBA
 +
|-
 +
|30
 +
|DBP
 +
|-
 +
|31
 +
|EMCP
 +
|}
 +
 +
=== HID1 ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-26
 +
|Reserved
 +
|-
 +
|27
 +
|PC4
 +
|-
 +
|28
 +
|PC3
 +
|-
 +
|29
 +
|PC2
 +
|-
 +
|30
 +
|PC1
 +
|-
 +
|31
 +
|PC0
 +
|}
 +
 +
=== HID2 ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-15
 +
|Reserved
 +
|-
 +
|16
 +
|DQOEE
 +
|-
 +
|17
 +
|DCMEE
 +
|-
 +
|18
 +
|DNCEE
 +
|-
 +
|19
 +
|DCHEE
 +
|-
 +
|20
 +
|DQOERR
 +
|-
 +
|21
 +
|DCMERR
 +
|-
 +
|22
 +
|DNCERR
 +
|-
 +
|23
 +
|DCHERR
 +
|-
 +
|24-27
 +
|DMAQL
 +
|-
 +
|28
 +
|LCE
 +
|-
 +
|29
 +
|PSE
 +
|-
 +
|30
 +
|WPE
 +
|-
 +
|31
 +
|LSQE
 +
|}
 +
 +
=== HID4 ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-19
 +
|Reserved
 +
|-
 +
|20
 +
|L2CFI
 +
|-
 +
|21
 +
|L2MUM
 +
|-
 +
|22
 +
|DBP
 +
|-
 +
|23
 +
|LPE
 +
|-
 +
|24
 +
|ST0
 +
|-
 +
|25
 +
|SBE
 +
|-
 +
|26
 +
|Reserved
 +
|-
 +
|27-28
 +
|BPD
 +
|-
 +
|29-30
 +
|L2FM
 +
|-
 +
|31
 +
|H4A
 +
|}
 +
 +
=== HID5 ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-24
 +
|Reserved
 +
|-
 +
|25
 +
|Enable UDMA
 +
|-
 +
|26-28
 +
|Reserved
 +
|-
 +
|29
 +
|Enable PIR
 +
|-
 +
|31
 +
|Enable HID5
 +
|}
 +
 +
=== SCR ===
 +
{| class="wikitable"
 +
!|Bits
 +
!|Description
 +
|-
 +
|0-17
 +
|Reserved
 +
|-
 +
|18
 +
|Core0 has a pending ICI
 +
|-
 +
|19
 +
|Core1 has a pending ICI
 +
|-
 +
|20
 +
|Core2 has a pending ICI
 +
|-
 +
|21
 +
|Enable Core2
 +
|-
 +
|22
 +
|Enable Core1
 +
|-
 +
|23-24
 +
|Reserved
 +
|-
 +
|25
 +
|If unset when booting from alternate ancast keys, errors and loops forever.
 +
|-
 +
|26
 +
|If bit26 and bit27 are set, uses vWii ancast keys.
 +
|-
 +
|27
 +
|If bit27 and bit26 are set, uses vWii ancast keys.
 +
|-
 +
|28
 +
|Keystore 20..3f enabled (clear only). Set just after reading provisioning u32?
 +
|-
 +
|29
 +
|Keystore 00..1f enabled (clear only)
 +
|-
 +
|30
 +
|Bootrom enabled (clear only)
 +
|-
 +
|31
 +
|Set before exiting bootrom? If somehow set before then, uses a secret alternate set of ancast keys and prod ECC?
 +
|}
 +
 +
== vWii Mode Clock ==
 +
While entering in vWii mode, Cafe2Wii reboots the PPC and sets the clock multiplier to 3x.
 +
This can be disabled by changing in Cafe2Wii an '''OR 0x20''' to '''BIC 0x20''' in [[Hardware/Latte_Registers|LT_MEMCMPT]] and an '''OR 0x99''' to '''OR 0x9D''' in [[Hardware/Latte_Registers|LT_SYSPROT]].
 +
[[Category:Hardware]]
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/2533...3905"