Line 47:
Line 47:
|
|
*[[Hardware/Latte Registers|Latte Registers]]
*[[Hardware/Latte Registers|Latte Registers]]
−
**[[Hardware/OTP|OTP]]
+
*[[Hardware/AHM controller|AHM Controller]]
−
*[[Hardware/Memory Controller|Memory Controller]]
+
*[[Hardware/Memory controller|Memory Controller]]
−
*[[Hardware/NAND Interface|NAND Interface]]
+
*[[Hardware/NAND interface|NAND Interface]]
−
*[[Hardware/AES Engine|AES Engine]]
+
*[[Hardware/AES engine|AES Engine]]
−
*[[Hardware/SHA-1 Engine|SHA-1 Engine]]
+
*[[Hardware/SHA-1 engine|SHA-1 Engine]]
*[[Hardware/USB Host Controller|USB Host Controller]]
*[[Hardware/USB Host Controller|USB Host Controller]]
*[[Hardware/SD Host Controller|SD Host Controller]]
*[[Hardware/SD Host Controller|SD Host Controller]]
*[[Hardware/802.11 Wireless|802.11 Wireless]]
*[[Hardware/802.11 Wireless|802.11 Wireless]]
−
*[[Hardware/SATA Controller|SATA Controller]]
+
*[[Hardware/SATA controller|SATA Controller]]
−
*[[Hardware/XN Controller|XN Controller]]
|
|
*[[Hardware/GX2|GX2 GPU]]
*[[Hardware/GX2|GX2 GPU]]
Line 62:
Line 61:
|
|
*[[Hardware/Latte Registers|Latte Registers]]
*[[Hardware/Latte Registers|Latte Registers]]
−
**[[Hardware/IPC|Inter-processor Communication]]
+
**[[Hardware/Latte IPC|Latte IPC]]
**[[Hardware/Latte GPIOs|Latte GPIOs]]
**[[Hardware/Latte GPIOs|Latte GPIOs]]
**[[Hardware/Latte IRQs|Latte IRQs]]
**[[Hardware/Latte IRQs|Latte IRQs]]
Line 68:
Line 67:
*[[Hardware/Legacy|Legacy Interfaces]]
*[[Hardware/Legacy|Legacy Interfaces]]
|
|
+
*[[Hardware/eFuse|eFuse]]
*[[Hardware/SEEPROM|Serial EEPROM]]
*[[Hardware/SEEPROM|Serial EEPROM]]
*[[Hardware/TSOP NAND|TSOP NAND Flash]]
*[[Hardware/TSOP NAND|TSOP NAND Flash]]