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Cafe OS (view source)

Revision as of 14:06, 25 January 2025

3,774 bytes added ,  25 January
→‎ReadRegister32Ex: describe other legacy register blocks
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| 0x4300 || LogRetrieve || X || X || X || X
 
| 0x4300 || LogRetrieve || X || X || X || X
 
|-
 
|-
−
| 0x4400 || || X || X || X ||  
+
| 0x4400 || LoadUserContext || X || X || X ||  
 
|-
 
|-
−
| 0x4500 || || X || X || X ||  
+
| 0x4500 || FlushUserContext || X || X || X ||  
 
|-
 
|-
−
| 0x4600 || || X || X || X ||  
+
| 0x4600 || FlushUserFPUContext || X || X || X ||  
 
|-
 
|-
 
| 0x4700 || Drivers_CopyFromSaveArea || X || X || X ||  
 
| 0x4700 || Drivers_CopyFromSaveArea || X || X || X ||  
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| 0x4900 || Proc_ReadyToRelease || X || X || X ||  
 
| 0x4900 || Proc_ReadyToRelease || X || X || X ||  
 
|-
 
|-
−
| 0x4A00 || SetAlarm || X || X || X ||  
+
| 0x4A00 || FlushInterrupts || X || X || X ||  
 
|-
 
|-
 
| 0x4B00 || SetDABR || X || X || X ||  
 
| 0x4B00 || SetDABR || X || X || X ||  
Line 298: Line 298:  
|}
 
|}
   −
== FastCalls ==
+
== Fastcalls ==
−
FastCalls, on the other hand, are system calls that aren't routed through the dispatcher and can be accessed by any RAMPID.
+
Fastcalls, on the other hand, are system calls that aren't routed through the dispatcher and can be accessed by any RAMPID.
 
Attempting to access an unimplemented fastcall will redirect the code flow to syscall 0x0100 (AppPanic).
 
Attempting to access an unimplemented fastcall will redirect the code flow to syscall 0x0100 (AppPanic).
   Line 337: Line 337:  
| 0xD || SetPerformanceMonitor
 
| 0xD || SetPerformanceMonitor
 
|-
 
|-
−
| 0xE ||  
+
| 0xE || SetUserDMA
 
|-
 
|-
 
| 0xF || ReturnFromInterrupt
 
| 0xF || ReturnFromInterrupt
Line 343: Line 343:  
| 0x10 || FlushFPUContext
 
| 0x10 || FlushFPUContext
 
|-
 
|-
−
| 0x11 || ReadRegister32Ex
+
| 0x11 || [[#ReadRegister32Ex|ReadRegister32Ex]]
 
|-
 
|-
−
| 0x12 || WriteRegister32Ex
+
| 0x12 || [[#WriteRegister32Ex|WriteRegister32Ex]]
 
|-
 
|-
 
| 0x13 ||  
 
| 0x13 ||  
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| 0x14 ||  
 
| 0x14 ||  
 
|-
 
|-
−
| 0x15 ||  
+
| 0x15 || WriteGatherInitWritePtr
 
|-
 
|-
 
| 0x16 ||  
 
| 0x16 ||  
 
|-
 
|-
−
| 0x17 ||  
+
| 0x17 || WriteGatherReadWritePtr
 
|-
 
|-
 
| 0x18 || EnableFPU
 
| 0x18 || EnableFPU
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| 0x1A-0x1F || BadFastCall (jump to error on purpose)
 
| 0x1A-0x1F || BadFastCall (jump to error on purpose)
 
|}
 
|}
 +
 +
=== ReadRegister32Ex ===
 +
Takes two u32s '''WhitelistIndex''' and '''RegisterIndex'''. Returns an u32 '''RegisterValue'''.
 +
 +
Reads a hardware register from the following whitelist:
 +
0                // Invalid
 +
0xFD020068      // 2 registers at 0x0D000068 (HW_I2CIOPINTEN to HW_I2CIOPINTSTS)
 +
0xFD0100C0      // 1 registers at 0x0D0000C0 (HW_GPIOPPCOUT)
 +
0xFD04021C      // 4 registers at 0x0D00021C
 +
0xFD040250      // 4 registers at 0x0D000250 (HW_I2CMCTRL to HW_I2CMDATARD)
 +
0xFD060520      // 6 registers at 0x0D000520 (LT_GPIOPPCOUT to LT_GPIOPPCINTEN)
 +
0xFD106400      // 16 registers at 0x0D006400 (SI0_OUTBUF to SIEXI_LOCK)
 +
0xFD046C00      // 4 registers at 0x0D006C00 (AI_CR to AI_IT)
 +
0xFD046E00      // 4 registers at 0x0D006E00
 +
0xFD0F6800      // 15 registers at 0x0D006800 (EXI0_CSR to EXI2_DATA)
 +
0                // Invalid
 +
0                // Invalid
 +
0                // Invalid
 +
0                // Invalid
 +
0                // Invalid
 +
0                // Invalid
 +
 +
=== WriteRegister32Ex ===
 +
Takes three u32s '''WhitelistIndex''', '''RegisterIndex''' and '''RegisterValue'''. No output.
 +
 +
Same as [[#ReadRegister32Ex|ReadRegister32Ex]], but for writing to a whitelisted hardware register instead.
    
== OSPlatformInfo ==
 
== OSPlatformInfo ==
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| 0x370 || 0x4 || HardwareVersion
 
| 0x370 || 0x4 || HardwareVersion
 
|-
 
|-
−
| 0x374 || 0x8C || Reserved
+
| 0x374 || 0x40 || Reserved
 +
|-
 +
| 0x3B4 || 0x4 || SmdBaseAddress
 +
|-
 +
| 0x3B8 || 0x48 || Reserved
 
|-
 
|-
 
| 0x400 || 0x4 || LastPMState
 
| 0x400 || 0x4 || LastPMState
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| 0x9C || 0x4 || Srr1
 
| 0x9C || 0x4 || Srr1
 
|-
 
|-
−
| 0xA0 || 0x10 ||  
+
| 0xA0 || 0x4 || Dsisr
 +
|-
 +
| 0xA4 || 0x4 || Dar
 +
|-
 +
| 0xA8 || 0x4 || CrashType
 +
|-
 +
| 0xAC || 0x4 || Reserved
 
|-
 
|-
 
| 0xB0 || 0x4 || FpscrHigh
 
| 0xB0 || 0x4 || FpscrHigh
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! Offset || Size || Description
 
! Offset || Size || Description
 
|-
 
|-
−
| 0x0 || 0x58 ||  
+
| 0x0 || 0x40 ||  
 +
|-
 +
| 0x40 || 0x4 || BootStage
 +
|-
 +
| 0x44 || 0x4 || CoreInitFunc
 +
|-
 +
| 0x48 || 0x4 || CoreState
 +
|-
 +
| 0x4C || 0x4 ||
 +
|-
 +
| 0x50 || 0x4 ||
 +
|-
 +
| 0x54 || 0x4 || IsKernelPanic
 
|-
 
|-
 
| 0x58 || 0x4 || InterruptedContext
 
| 0x58 || 0x4 || InterruptedContext
 
|-
 
|-
−
| 0x5C || 0x4 ||  
+
| 0x5C || 0x4 || CurrentFpuContext
 
|-
 
|-
−
| 0x60 || 0x4 ||  
+
| 0x60 || 0x4 || CurrentCoreControl
 
|-
 
|-
 
| 0x64 || 0x4 || SysCallTableAddress
 
| 0x64 || 0x4 || SysCallTableAddress
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| 0x68 || 0x4 || FastCallBaseAddress
 
| 0x68 || 0x4 || FastCallBaseAddress
 
|-
 
|-
−
| 0x6C || 0x20 ||  
+
| 0x6C || 0x4 || NonRecoverableExceptionHandlerTableAddress
 +
|-
 +
| 0x70 || 0x4 || RecoverableExceptionHandlerTableAddress
 +
|-
 +
| 0x74 || 0x2 ||
 +
|-
 +
| 0x76 || 0x2 ||
 +
|-
 +
| 0x78 || 0x4 || LoadPerfMonContext
 +
|-
 +
| 0x7C || 0x4 || CurrentSysCallAddress
 +
|-
 +
| 0x80 || 0x4 || CurrentSysCallCallback
 +
|-
 +
| 0x84 || 0x4 || NonRecoverableExceptionContextAddress
 +
|-
 +
| 0x88 || 0x4 || RecoverableExceptionContextAddress
 
|-
 
|-
 
| 0x8C || 0x4 || NormalSysCalls
 
| 0x8C || 0x4 || NormalSysCalls
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| 0x98 || 0x4 || IciExceptions
 
| 0x98 || 0x4 || IciExceptions
 
|-
 
|-
−
| 0x9C || 0xC ||  
+
| 0x9C || 0x4 ||  
 +
|-
 +
| 0xA0 || 0x4 || Ps0
 +
|-
 +
| 0xA4 || 0x4 || Ps1
 +
|-
 +
| 0xA8 || 0x8 || ProcessWork
 
|-
 
|-
−
| 0xA8 || 0xC || ProcessWork
+
| 0xB0 || 0x4 ||  
 
|-
 
|-
−
| 0xB4 || 0x4 || TotalProcesses
+
| 0xB4 || 0x4 || RamPid
 
|-
 
|-
−
| 0xB8 || 0x4 || ProcessIndex
+
| 0xB8 || 0x4 || Upid
 
|-
 
|-
−
| 0xBC || 0x4 ||  
+
| 0xBC || 0x4 || Mem1Address
 
|-
 
|-
 
| 0xC0 || 0x4 || InterceptedLoadContext
 
| 0xC0 || 0x4 || InterceptedLoadContext
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| 0xC8 || 0x4 || AddrConfig
 
| 0xC8 || 0x4 || AddrConfig
 
|-
 
|-
−
| 0xCC || 0x20 ||  
+
| 0xCC || 0x20 || SysCallCallbackGpr
 
|-
 
|-
 
| 0xEC || 0x4 || EaDataBegin
 
| 0xEC || 0x4 || EaDataBegin
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| 0xF0 || 0x4 || EaDataEnd
 
| 0xF0 || 0x4 || EaDataEnd
 
|-
 
|-
−
| 0xF4 || 0x78 ||  
+
| 0xF4 || 0x18 ||  
 +
|-
 +
| 0x10C || 0x4 || WriteGatherDataOffset
 +
|-
 +
| 0x110 || 0x30 || [[#ExceptionInfo|ExceptionInfo]]
 +
|-
 +
| 0x140 || 0x4 || OverwriteGprOnExceptionExit
 +
|-
 +
| 0x144 || 0x28 || ExceptionExitGpr
 
|-
 
|-
 
| 0x16C || 0x28 || [[#PostException|PostException]]
 
| 0x16C || 0x28 || [[#PostException|PostException]]
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| 0x194 || 0x4 ||  
 
| 0x194 || 0x4 ||  
 
|-
 
|-
−
| 0x198 || 0x140 || [[#ExceptionContext|ExceptionContext0]]
+
| 0x198 || 0x128 || [[#ExceptionContext|RecoverableExceptionContext]]
 
|-
 
|-
−
| 0x2D8 || 0x140 || [[#ExceptionContext|ExceptionContext1]]
+
| 0x2C0 || 0x14 ||
 +
|-
 +
| 0x2D8 || 0x128 || [[#ExceptionContext|NonRecoverableExceptionContext]]
 
|}
 
|}
   Line 627: Line 707:  
| 0x9C || 0x4 || Srr1
 
| 0x9C || 0x4 || Srr1
 
|-
 
|-
−
| 0xA0 || 0xA0 ||  
+
| 0xA0 || 0x88 ||  
 +
|}
 +
 
 +
== ExceptionInfo ==
 +
{| class="wikitable" border="1"
 +
|-
 +
! Offset || Size || Description
 +
|-
 +
| 0x0 || 0x4 ||
 +
|-
 +
| 0x4 || 0x4 ||
 +
|-
 +
| 0x8 || 0x4 || UserStackPtr
 +
|-
 +
| 0xC || 0x4 || ExHandler
 +
|-
 +
| 0x10 || 0x4 || Msr
 +
|-
 +
| 0x14 || 0x4 || Sprg0
 +
|-
 +
| 0x18 || 0x4 || Dsisr
 +
|-
 +
| 0x1C || 0x4 || Dar
 +
|-
 +
| 0x20 || 0x4 ||
 +
|-
 +
| 0x24 || 0x4 ||
 +
|-
 +
| 0x28 || 0x4 ||
 +
|-
 +
| 0x2C || 0x4 || CallbackContext
 
|}
 
|}
   Line 654: Line 764:  
|-
 
|-
 
| 0x24 || 0x4 ||  
 
| 0x24 || 0x4 ||  
 +
|}
 +
 +
== NewExecCtx ==
 +
{| class="wikitable" border="1"
 +
|-
 +
! Offset || Size || Description
 +
|-
 +
| 0x0 || 0x4 || InterruptedContext
 +
|-
 +
| 0x4 || 0x4 || CurrentFpuContext
 +
|-
 +
| 0x8 || 0x4 ||
 +
|-
 +
| 0xC || 0x4 || FastCallBaseAddress
 +
|-
 +
| 0x10 || 0x4 || SintEnableAfterKernelExit
 +
|-
 +
| 0x14 || 0x4 ||
 +
|-
 +
| 0x18 || 0x4 ||
 +
|-
 +
| 0x1C || 0x4 || Dabr
 +
|-
 +
| 0x20 || 0x4 || Iabr
 +
|-
 +
| 0x24 || 0x4 || EaDataBegin
 +
|-
 +
| 0x24 || 0x4 || EaDataEnd
 +
|-
 +
| 0x28 || 0x1C ||
 +
|-
 +
| 0x48 || 0x4 || AddrConfig
 +
|-
 +
| 0x4C || 0x3C || [[#PerCore|PerCore]]
 +
|}
 +
 +
== PerCore ==
 +
This is a structure mapped to address 0xFFFFFFC0.
 +
 +
{| class="wikitable" border="1"
 +
|-
 +
! Offset || Size || Description
 +
|-
 +
| 0x0 || 0x18 ||
 +
|-
 +
| 0x18 || 0x4 || UserHeartBeat
 +
|-
 +
| 0x1C || 0x4 ||
 +
|-
 +
| 0x20 || 0x4 || CurrentThread
 +
|-
 +
| 0x24 || 0x4 || SoftIntEnabled
 +
|-
 +
| 0x28 || 0x4 || SoftIntPending
 +
|-
 +
| 0x2C || 0x4 || CurrentContext
 +
|-
 +
| 0x30 || 0x4 ||
 +
|-
 +
| 0x34 || 0x4 ||
 +
|-
 +
| 0x38 || 0x4 || ThreadQueue
 
|}
 
|}
   Line 958: Line 1,130:  
| 0xC2A0000
 
| 0xC2A0000
 
| 0x78100023
 
| 0x78100023
−
| Write Pipe
+
| Write Gather Pipe
 
|-
 
|-
 
| 0xFC300000
 
| 0xFC300000
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Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/3887...4140"