(Created page with "{{Infobox MMIO | ppc = None | arm = Full | base = 0x0d8b0800 | len = 0x800 | bits = 32 | ppcirq = ??? | latteirq = ??? }} Similarly to the [[Hardware/Memory_Controller|memory...") |
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+ | = AHM = | ||
{{Infobox MMIO | {{Infobox MMIO | ||
− | | | + | | title = AHM controller |
+ | | arm = Full | ||
+ | | base = 0x0d8b0000 | ||
+ | | len = 0x800 | ||
+ | | bits = 32 | ||
+ | | ppcirq = ??? | ||
+ | | latteirq = ??? | ||
+ | }} | ||
+ | |||
+ | AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the [[Hardware/Memory Controller|Memory Controller]]. | ||
+ | |||
+ | == Register List == | ||
+ | {{reglist|AHM controller}} | ||
+ | {{rld|0x0d8b0000|32|AHM_SECDDR|AHM DDR memory security}} | ||
+ | {{rld|0x0d8b0004|32|AHM_SECSPL|AHM SPLASH memory security}} | ||
+ | {{rld|0x0d8b0008|32|AHM_RDBI|AHM read data buffer invalidate mask}} | ||
+ | {{rld|0x0d8b0010|32|AHM_PREFCFG|AHM prefetch configuration}} | ||
+ | {{rld|0x0d8b0020|32|AHM_INTMSK|AHM interrupt mask}} | ||
+ | {{rld|0x0d8b0030|32|AHM_INTSTS|AHM interrupt status}} | ||
+ | {{rld|0x0d8b0040|32|UNKNOWN|Unknown}} | ||
+ | {{rld|0x0d8b0044|32|UNKNOWN|Unknown}} | ||
+ | {{rld|0x0d8b0100...0x0d8b0300|32|AHM_PROTDDR|Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR)}} | ||
+ | {{rld|0x0d8b0500...0x0d8b0700|32|AHM_PROTSPL|Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL)}} | ||
+ | |} | ||
+ | |||
+ | == Register Details == | ||
+ | |||
+ | = AMN = | ||
+ | The Latte hardware contains an enhanced version of AHB_MEM dubbed AMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S). | ||
+ | |||
+ | {{Infobox MMIO | ||
+ | | title = AMN controller | ||
| arm = Full | | arm = Full | ||
| base = 0x0d8b0800 | | base = 0x0d8b0800 | ||
Line 8: | Line 40: | ||
| latteirq = ??? | | latteirq = ??? | ||
}} | }} | ||
− | |||
− | |||
− | |||
== Register List == | == Register List == | ||
− | {{reglist| | + | {{reglist|AMN controller}} |
− | {{rld|0x0d8b0800|32| | + | {{rld|0x0d8b0800|32|AMN_SECMEM0|AMN MEM0 memory security}} |
− | {{rld|0x0d8b0804|32| | + | {{rld|0x0d8b0804|32|AMN_SECMEM1|AMN MEM1 memory security}} |
− | {{rld|0x0d8b0808|32| | + | {{rld|0x0d8b0808|32|AMN_SECMEM2|AMN MEM2 memory security}} |
− | {{rld|0x0d8b080c|32| | + | {{rld|0x0d8b080c|32|AMN_RDBI|AMN read data buffer invalidate mask}} |
− | {{rld|0x0d8b0820|32| | + | {{rld|0x0d8b0820|32|AMN_INTMSK|AMN interrupt mask}} |
− | {{rld|0x0d8b0824|32| | + | {{rld|0x0d8b0824|32|AMN_INTSTS|AMN interrupt status}} |
− | {{rld|0x0d8b0840|32| | + | {{rld|0x0d8b0840|32|UNKNOWN|Unknown}} |
− | {{rld|0x0d8b0844|32| | + | {{rld|0x0d8b0844|32|UNKNOWN|Unknown}} |
− | {{rld|0x0d8b0850|32| | + | {{rld|0x0d8b0850|32|AMN_MWTSTS|AHMN transfer status}} |
− | {{rld|0x0d8b0854|32| | + | {{rld|0x0d8b0854|32|AMN_WORKAROUND|Unknown}} |
− | {{rld|0x0d8b0900...0x0d8b0980|32| | + | {{rld|0x0d8b0860|32|AMN_MWTFLSH|Unknown}} |
− | {{rld|0x0d8b0a00...0x0d8b0c00|32| | + | {{rld|0x0d8b0900...0x0d8b0980|32|AMN_MEM0PROT|Each register controls access protection for one page of MEM0 memory (page size depends on AMN_SECMEM0)}} |
− | {{rld|0x0d8b0c00...0x0d8b1000|32| | + | {{rld|0x0d8b0a00...0x0d8b0c00|32|AMN_MEM1PROT|Each register controls access protection for one page of MEM1 memory (page size depends on AMN_SECMEM1)}} |
+ | {{rld|0x0d8b0c00...0x0d8b1000|32|AMN_MEM2PROT|Each register controls access protection for one page of MEM2 memory (page size depends on AMN_SECMEM2)}} | ||
|} | |} | ||
== Register Details == | == Register Details == |
Latest revision as of 22:30, 20 April 2025
AHM
AHM controller | |
Access | |
---|---|
Espresso | None |
Starbuck | Full |
Registers | |
Base | 0x0d8b0000 |
Length | 0x800 |
Access size | 32 bits |
Byte order | Big Endian |
IRQs | |
Espresso | ??? |
Latte | ??? |
AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the Memory Controller.
Register List
AHM controller | |||
---|---|---|---|
Address | Bits | Name | Description |
0x0d8b0000 | 32 | AHM_SECDDR | AHM DDR memory security |
0x0d8b0004 | 32 | AHM_SECSPL | AHM SPLASH memory security |
0x0d8b0008 | 32 | AHM_RDBI | AHM read data buffer invalidate mask |
0x0d8b0010 | 32 | AHM_PREFCFG | AHM prefetch configuration |
0x0d8b0020 | 32 | AHM_INTMSK | AHM interrupt mask |
0x0d8b0030 | 32 | AHM_INTSTS | AHM interrupt status |
0x0d8b0040 | 32 | UNKNOWN | Unknown |
0x0d8b0044 | 32 | UNKNOWN | Unknown |
0x0d8b0100...0x0d8b0300 | 32 | AHM_PROTDDR | Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR) |
0x0d8b0500...0x0d8b0700 | 32 | AHM_PROTSPL | Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL) |
Register Details
AMN
The Latte hardware contains an enhanced version of AHB_MEM dubbed AMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).
AMN controller | |
Access | |
---|---|
Espresso | None |
Starbuck | Full |
Registers | |
Base | 0x0d8b0800 |
Length | 0x800 |
Access size | 32 bits |
Byte order | Big Endian |
IRQs | |
Espresso | ??? |
Latte | ??? |
Register List
AMN controller | |||
---|---|---|---|
Address | Bits | Name | Description |
0x0d8b0800 | 32 | AMN_SECMEM0 | AMN MEM0 memory security |
0x0d8b0804 | 32 | AMN_SECMEM1 | AMN MEM1 memory security |
0x0d8b0808 | 32 | AMN_SECMEM2 | AMN MEM2 memory security |
0x0d8b080c | 32 | AMN_RDBI | AMN read data buffer invalidate mask |
0x0d8b0820 | 32 | AMN_INTMSK | AMN interrupt mask |
0x0d8b0824 | 32 | AMN_INTSTS | AMN interrupt status |
0x0d8b0840 | 32 | UNKNOWN | Unknown |
0x0d8b0844 | 32 | UNKNOWN | Unknown |
0x0d8b0850 | 32 | AMN_MWTSTS | AHMN transfer status |
0x0d8b0854 | 32 | AMN_WORKAROUND | Unknown |
0x0d8b0860 | 32 | AMN_MWTFLSH | Unknown |
0x0d8b0900...0x0d8b0980 | 32 | AMN_MEM0PROT | Each register controls access protection for one page of MEM0 memory (page size depends on AMN_SECMEM0) |
0x0d8b0a00...0x0d8b0c00 | 32 | AMN_MEM1PROT | Each register controls access protection for one page of MEM1 memory (page size depends on AMN_SECMEM1) |
0x0d8b0c00...0x0d8b1000 | 32 | AMN_MEM2PROT | Each register controls access protection for one page of MEM2 memory (page size depends on AMN_SECMEM2) |