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| − | {{Infobox MMIO
| + | #REDIRECT [[Hardware/Espresso]] |
| − | | arm = Full
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| − | | ppc = Full
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| − | | base = 0x0C000000
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| − | | len = 0x400000
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| − | | bits = 32
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| − | | ppcirq = ??
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| − | | latteirq = ??
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| − | }}
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| − | | |
| − | ==Register List==
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| − | {{reglist|Espresso Registers}}
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| − | {{rld|0x0C206084|32|FB0_STATE|Controls TV framebuffer state.|drs=1}}
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| − | {{rld|0x0C206100|32|FB0_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
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| − | {{rld|0x0C206104|32|FB0_MODE|Controls TV framebuffer mode.|drs=1}}
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| − | {{rld|0x0C206110|32|FB0_ADDR|Physical memory location of TV framebuffer.|drs=1}}
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| − | {{rld|0x0C206120|32|FB0_WIDTH1|Width of TV framebuffer.|drs=2}}
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| − | {{rld|0x0C206198|32|FB0_WIDTH2}}
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| − | {{rld|0x0C206914|32|FB0_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
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| − | {{rld|0x0C207084|32|FB1_STATE|Controls TV framebuffer state.|drs=1}}
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| − | {{rld|0x0C207100|32|FB1_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
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| − | {{rld|0x0C207104|32|FB1_MODE|Controls TV framebuffer mode.|drs=1}}
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| − | {{rld|0x0C207110|32|FB1_ADDR|Physical memory location of TV framebuffer.|drs=1}}
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| − | {{rld|0x0C207120|32|FB1_WIDTH1|Width of TV framebuffer.|drs=2}}
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| − | {{rld|0x0C207198|32|FB1_WIDTH2}}
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| − | {{rld|0x0C207914|32|FB1_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
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| − | |}
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| − | | |
| − | ==Framebuffer Registers==
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| − | {{reg32|FB''x''_STATE|addr=0x0C206084/0x0C207084|hifields=1|lofields=3|
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| − | |16 |
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| − | |U |
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| − | | ||
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| − | |7|1 |8|
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| − | |U|RW |U|
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| − | | |DSBL| |
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| − | }}
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| − | {{regdesc
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| − | |DSBL|Set to ''disable'' the buffer, and clear to ''enable'' it.
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| − | }}
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| − | | |
| − | {{reg32|FB''x''_MODE_UPDATE|addr=0x0C206100/0x0C207100|hifields=1|lofields=2|
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| − | |16 |
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| − | |U |
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| − | | ||
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| − | |15|1 |
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| − | |U |W |
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| − | | |UPD|
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| − | }}
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| − | {{regdesc
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| − | |UPD|Must be set directly after '''FB''x''_MODE''' changes.{{check}}
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| − | }}
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| − | This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_MODE''' writes.
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| − | | |
| − | | |
| − | {{reg32|FB''x''_MODE|addr=0x0C206104/0x0C207104|hifields=3|lofields=4|
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| − | |8 |4 |4 |
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| − | |U |RW |U |
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| − | | |UNK1 | ||
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| − | |5|3 |6|2 |
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| − | |U|RW |U|RW |
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| − | | |UNK2| |UNK3|
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| − | }}
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| − | {{regdesc
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| − | |UNK1|Unknown. Bit 20 (0x100000) set during OSScreen initialisation.
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| − | |UNK2|Unknown. All bits cleared during OSScreen initialisation.
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| − | |UNK3|Unknown. Bit 1 (0x2) set during OSScreen initialisation.
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| − | }}
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| − | A simplified view of how OSScreen sets up this register is as follows:
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| − | <syntaxhighlight lang="c">
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| − | *FBx_MODE = (*FBx_MODE & 0xFF0FF8FC) | 0x100002;
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| − | </syntaxhighlight>
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| − | | |
| − | | |
| − | {{reg32|FB''x''_ADDR|addr=0x0C206110/0x0C207110|hifields=1|lofields=3|
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| − | |16 |
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| − | |W |
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| − | |ADDR ||
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| − | |8 |7|1 |
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| − | |W |U|W |
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| − | |ADDR| |UNK|
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| − | }}
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| − | {{regdesc
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| − | |ADDR|High 24 bits of physical address for displayed framebuffer.
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| − | |UNK |Unknown. Set during OSScreen initialisation.
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| − | }}
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| − | | |
| − | {{reg32|FB''x''_WIDTH''x''|addr=0x0C206120/0x0C206198/0x0C207120/0x0C207198|hifields=1|lofields=2|
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| − | |16 |
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| − | |U |
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| − | | ||
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| − | |2|14|
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| − | |U|W |
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| − | | |PX|
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| − | }}
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| − | {{regdesc
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| − | |PX|Target width of framebuffer in pixels.
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| − | }}
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| − | It's not known why there appears to be two of these registers for each framebuffer. OSScreen writes an identical value to each.
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| − | | |
| − | | |
| − | {{reg32|FB''x''_ADDR_UPDATE|addr=0x0C206914/0x0C207914|hifields=1|lofields=1|
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| − | |16 |
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| − | |U |
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| − | | ||
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| − | |16 |
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| − | |U |
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| − | | |
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| − | }}
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| − | {{regdesc
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| − | |FB''x''_ADDR_UPDATE|All bits cleared during OSScreen initialisation.
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| − | }}
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| − | This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_ADDR''' writes.
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