Changes

Note that, since the interrupts can actually route to either or both the Starbuck and Espresso, and since the Starbuck can also access the Espresso's registers, there are ways of abusing these flags for odd purposes.

Note that, since the interrupts can actually route to either or both the Starbuck and Espresso, and since the Starbuck can also access the Espresso's registers, there are ways of abusing these flags for odd purposes.

Register HW_IPC_ARMCTRL can only be accessed by the Starbuck. The other three registers can be accessed by both CPUs.

Register LT_IPC_ARMCTRL can only be accessed by the Starbuck. The other three registers can be accessed by both CPUs.

== Register List ==

== Register List ==

===Global ARM block===

===Global ARM block===

{{reglist|Global ARM block}}

{{reglist|Global ARM block}}

{{rla|0x0d800000|32|HW_IPC_PPCMSG|Espresso data register}}

{{rla|0x0d800000|32|LT_IPC_PPCMSG|Espresso data register}}

{{rla|0x0d800004|32|HW_IPC_PPCCTRL|Espresso flags and control}}

{{rla|0x0d800004|32|LT_IPC_PPCCTRL|Espresso flags and control}}

{{rla|0x0d800008|32|HW_IPC_ARMMSG|Starbuck data register}}

{{rla|0x0d800008|32|LT_IPC_ARMMSG|Starbuck data register}}

{{rla|0x0d80000c|32|HW_IPC_ARMCTRL|Starbuck flags and control}}

{{rla|0x0d80000c|32|LT_IPC_ARMCTRL|Starbuck flags and control}}

|}

|}

===SMP block===

===SMP block===

{{reglist|SMP block - PPC core 0}}

{{reglist|SMP block - PPC core 0}}

{{rla|0x0d800400|32|HW_IPC_PPC0_PPCMSG|Espresso data register for PPC core 0}}

{{rla|0x0d800400|32|LT_IPC_PPC0_PPCMSG|Espresso data register for PPC core 0}}

{{rla|0x0d800404|32|HW_IPC_PPC0_PPCCTRL|Espresso flags and control for PPC core 0}}

{{rla|0x0d800404|32|LT_IPC_PPC0_PPCCTRL|Espresso flags and control for PPC core 0}}

{{rla|0x0d800408|32|HW_IPC_PPC0_ARMMSG|Starbuck data register for PPC core 0}}

{{rla|0x0d800408|32|LT_IPC_PPC0_ARMMSG|Starbuck data register for PPC core 0}}

{{rla|0x0d80040c|32|HW_IPC_PPC0_ARMCTRL|Starbuck flags and control for PPC core 0}}

{{rla|0x0d80040c|32|LT_IPC_PPC0_ARMCTRL|Starbuck flags and control for PPC core 0}}

|}

|}

{{reglist|SMP block - PPC core 1}}

{{reglist|SMP block - PPC core 1}}

{{rla|0x0d800410|32|HW_IPC_PPC1_PPCMSG|Espresso data register for PPC core 1}}

{{rla|0x0d800410|32|LT_IPC_PPC1_PPCMSG|Espresso data register for PPC core 1}}

{{rla|0x0d800414|32|HW_IPC_PPC1_PPCCTRL|Espresso flags and control for PPC core 1}}

{{rla|0x0d800414|32|LT_IPC_PPC1_PPCCTRL|Espresso flags and control for PPC core 1}}

{{rla|0x0d800418|32|HW_IPC_PPC1_ARMMSG|Starbuck data register for PPC core 1}}

{{rla|0x0d800418|32|LT_IPC_PPC1_ARMMSG|Starbuck data register for PPC core 1}}

{{rla|0x0d80041c|32|HW_IPC_PPC1_ARMCTRL|Starbuck flags and control for PPC core 1}}

{{rla|0x0d80041c|32|LT_IPC_PPC1_ARMCTRL|Starbuck flags and control for PPC core 1}}

|}

|}

{{reglist|SMP block - PPC core 2}}

{{reglist|SMP block - PPC core 2}}

{{rla|0x0d800420|32|HW_IPC_PPC2_PPCMSG|Espresso data register for PPC core 2}}

{{rla|0x0d800420|32|LT_IPC_PPC2_PPCMSG|Espresso data register for PPC core 2}}

{{rla|0x0d800424|32|HW_IPC_PPC2_PPCCTRL|Espresso flags and control for PPC core 2}}

{{rla|0x0d800424|32|LT_IPC_PPC2_PPCCTRL|Espresso flags and control for PPC core 2}}

{{rla|0x0d800428|32|HW_IPC_PPC2_ARMMSG|Starbuck data register for PPC core 2}}

{{rla|0x0d800428|32|LT_IPC_PPC2_ARMMSG|Starbuck data register for PPC core 2}}

{{rla|0x0d80042c|32|HW_IPC_PPC2_ARMCTRL|Starbuck flags and control for PPC core 2}}

{{rla|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL|Starbuck flags and control for PPC core 2}}

|}

|}

== Register Details ==

== Register Details ==

{{regsimple | HW_IPC_PPCMSG | addr = 0x0d800000 | bits = 32 | access = R/W }}

{{regsimple | LT_IPC_PPCMSG | addr = 0x0d800000 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

----

----

{{reg32 | HW_IPC_PPCCTRL | addr = 0x0d800004 | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPC_PPCCTRL | addr = 0x0d800004 | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|

===IOS usage===

===IOS usage===

{{regdesc

{{regdesc

|X1|Execute command: a new pointer is available ''in HW_IPC_PPCCTRL''

|X1|Execute command: a new pointer is available ''in LT_IPC_PPCCTRL''

|Y2|Command acknowledge

|Y2|Command acknowledge

|Y1|Command executed and reply available in ''HW_IPC_ARMMSG''

|Y1|Command executed and reply available in ''LT_IPC_ARMMSG''

|X2|Relaunch

|X2|Relaunch

}}

}}

----

----

{{regsimple | HW_IPC_ARMMSG | addr = 0x0d800008 | bits = 32 | access = R/W }}

{{regsimple | LT_IPC_ARMMSG | addr = 0x0d800008 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

----

----

{{reg32 | HW_IPC_ARMCTRL | addr = 0x0d80000c | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPC_ARMCTRL | addr = 0x0d80000c | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|