Changes

== Register List ==

== Register List ==

The Latte IPC engine has two different register blocks: a global ARM block mapped at the same address as on the Wii, and a new SMP block for each PPC core to use. Each core's region of the SMP block has registers equivalent to the global ARM block.

The Latte IPC engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores. Each core's region of the SMP block has registers equivalent to the old global block.

===Global ARM block===

===Compat block===

{{reglist|Global ARM block}}

{{reglist|Global compat block}}

{{rla|0x0d800000|32|LT_IPC_PPCMSG|Espresso data register}}

{{rla|0x0d800000|32|LT_IPC_PPCMSG_COMPAT|Espresso data register for vWii}}

{{rla|0x0d800004|32|LT_IPC_PPCCTRL|Espresso flags and control}}

{{rla|0x0d800004|32|LT_IPC_PPCCTRL_COMPAT|Espresso flags and control for vWii}}

{{rla|0x0d800008|32|LT_IPC_ARMMSG|Starbuck data register}}

{{rla|0x0d800008|32|LT_IPC_ARMMSG_COMPAT|Starbuck data register for vWii}}

{{rla|0x0d80000c|32|LT_IPC_ARMCTRL|Starbuck flags and control}}

{{rla|0x0d80000c|32|LT_IPC_ARMCTRL_COMPAT|Starbuck flags and control for vWii}}

|}

|}

== Register Details ==

== Register Details ==

{{regsimple | LT_IPC_PPCMSG | addr = 0x0d800000 | bits = 32 | access = R/W }}

{{regsimple | LT_IPC_PPCx_PPCMSG | addr = 0x0d800400/0x0d800410/0x0d800420 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].

----

----

{{reg32 | LT_IPC_PPCCTRL | addr = 0x0d800004 | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPC_PPCx_PPCCTRL | addr = 0x0d800404/0x0d800414/0x0d800424 | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|

===IOS usage===

===IOS usage===

{{regdesc

{{regdesc

|X1|Execute command: a new pointer is available ''in LT_IPC_PPCCTRL''

|X1|Execute command: a new pointer is available ''in LT_IPC_PPCx_PPCCTRL''

|Y2|Command acknowledge

|Y2|Command acknowledge

|Y1|Command executed and reply available in ''LT_IPC_ARMMSG''

|Y1|Command executed and reply available in ''LT_IPC_PPCx_ARMMSG''

|X2|Relaunch

|X2|Relaunch

}}

}}

----

----

{{regsimple | LT_IPC_ARMMSG | addr = 0x0d800008 | bits = 32 | access = R/W }}

{{regsimple | LT_IPC_PPCx_ARMMSG | addr = 0x0d800408/0x0d800418/0x0d800428 | bits = 32 | access = R/W }}

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.

----

----

{{reg32 | LT_IPC_ARMCTRL | addr = 0x0d80000c | hifields = 1 | lofields = 7 |

{{reg32 | LT_IPC_PPCx_ARMCTRL | addr = 0x0d80040c/0x0d80041c/0x0d80042c | hifields = 1 | lofields = 7 |

|16|

|16|

|U|

|U|