Difference between revisions of "Hardware/Processor interface"
< Hardware
Jump to navigation
Jump to search
Marionumber1 (talk | contribs) (Create basic Processor Interface page) |
Marionumber1 (talk | contribs) m (→Register List: Imported from Wiibrew IPC page, forgot to change "IPC" part) |
||
| Line 16: | Line 16: | ||
==Register List== | ==Register List== | ||
| − | {{reglist| | + | {{reglist|Processor Interface}} |
{{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}} | {{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}} | ||
{{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}} | {{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}} | ||
Revision as of 23:01, 20 August 2015
| Processor interface | |
| Access | |
|---|---|
| Espresso | Full |
| Starbuck | None |
| Registers | |
| Base | 0x0c000000 |
| Length | 0xc0000 |
| Access size | 32 bits |
| Byte order | Big Endian |
IRQ Sources
| IRQ | Description |
|---|---|
Register List
| Processor Interface | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0c000000 | 32 | PI_INTSR_GLOBAL | Globally-triggered IRQs |
| 0x0c000004 | 32 | PI_INTMR_GLOBAL | Globally-allowed IRQs |
| 0x0c000078 | 32 | PI_INTSR_CPU0 | Triggered IRQs for CPU0 |
| 0x0c00007c | 32 | PI_INTMR_CPU0 | Allowed IRQs for CPU0 |
| 0x0c000080 | 32 | PI_INTSR_CPU1 | Triggered IRQs for CPU1 |
| 0x0c000084 | 32 | PI_INTMR_CPU1 | Allowed IRQs for CPU1 |
| 0x0c000088 | 32 | PI_INTSR_CPU2 | Triggered IRQs for CPU2 |
| 0x0c00008c | 32 | PI_INTMR_CPU2 | Allowed IRQs for CPU2 |