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Hardware/Espresso Registers (view source)

Revision as of 13:54, 11 July 2017

2,571 bytes added ,  13:54, 11 July 2017
Add framebuffer registers
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{{Infobox MMIO
 
{{Infobox MMIO
−
| arm = ??
+
| arm = Full
−
| ppc = ??
+
| ppc = Full
 
| base = 0x0C000000
 
| base = 0x0C000000
 
| len = 0x400000
 
| len = 0x400000
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{{reglist|Espresso Registers}}
 
{{reglist|Espresso Registers}}
 
{{rld|0x0C206084|32|FB0_STATE|Controls TV framebuffer state.|drs=1}}
 
{{rld|0x0C206084|32|FB0_STATE|Controls TV framebuffer state.|drs=1}}
−
{{rld|0x0C206100|32|FB0_MODE_UPDATE|Update flag for TV framebuffer mode register.|drs=1}}
+
{{rld|0x0C206100|32|FB0_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
 
{{rld|0x0C206104|32|FB0_MODE|Controls TV framebuffer mode.|drs=1}}
 
{{rld|0x0C206104|32|FB0_MODE|Controls TV framebuffer mode.|drs=1}}
 
{{rld|0x0C206110|32|FB0_ADDR|Physical memory location of TV framebuffer.|drs=1}}
 
{{rld|0x0C206110|32|FB0_ADDR|Physical memory location of TV framebuffer.|drs=1}}
 
{{rld|0x0C206120|32|FB0_WIDTH1|Width of TV framebuffer.|drs=2}}
 
{{rld|0x0C206120|32|FB0_WIDTH1|Width of TV framebuffer.|drs=2}}
 
{{rld|0x0C206198|32|FB0_WIDTH2}}
 
{{rld|0x0C206198|32|FB0_WIDTH2}}
−
{{rld|0x0C206914|32|FB0_ADDR_UPDATE|Update flag for TV framebuffer (contested)|drs=1}}
+
{{rld|0x0C206914|32|FB0_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
 +
{{rld|0x0C207084|32|FB1_STATE|Controls TV framebuffer state.|drs=1}}
 +
{{rld|0x0C207100|32|FB1_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
 +
{{rld|0x0C207104|32|FB1_MODE|Controls TV framebuffer mode.|drs=1}}
 +
{{rld|0x0C207110|32|FB1_ADDR|Physical memory location of TV framebuffer.|drs=1}}
 +
{{rld|0x0C207120|32|FB1_WIDTH1|Width of TV framebuffer.|drs=2}}
 +
{{rld|0x0C207198|32|FB1_WIDTH2}}
 +
{{rld|0x0C207914|32|FB1_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
 
|}
 
|}
 +
 +
==Framebuffer Registers==
 +
{{reg32|FB''x''_STATE|addr=0x0C206084/0x0C207084|hifields=1|lofields=3|
 +
|16      |
 +
|U      |
 +
|        ||
 +
|7|1  |8|
 +
|U|RW  |U|
 +
| |DSBL| |
 +
}}
 +
{{regdesc
 +
|DSBL|Set to ''disable'' the buffer, and clear to ''enable'' it.
 +
}}
 +
 +
{{reg32|FB''x''_MODE_UPDATE|addr=0x0C206100/0x0C207100|hifields=1|lofields=2|
 +
|16    |
 +
|U    |
 +
|      ||
 +
|15|1  |
 +
|U |W  |
 +
|  |UPD|
 +
}}
 +
{{regdesc
 +
|UPD|Must be set directly after '''FB''x''_MODE''' changes.{{check}}
 +
}}
 +
This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_MODE''' writes.
 +
 +
 +
{{reg32|FB''x''_MODE|addr=0x0C206104/0x0C207104|hifields=3|lofields=4|
 +
|8  |4    |4  |
 +
|U  |RW  |U  |
 +
|  |UNK1 |  ||
 +
|5|3  |6|2  |
 +
|U|RW  |U|RW  |
 +
| |UNK2| |UNK3|
 +
}}
 +
{{regdesc
 +
|UNK1|Unknown. Bit 20 (0x100000) set during OSScreen initialisation.
 +
|UNK2|Unknown. All bits cleared during OSScreen initialisation.
 +
|UNK3|Unknown. Bit 1 (0x2) set during OSScreen initialisation.
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}}
 +
A simplified view of how OSScreen sets up this register is as follows:
 +
<syntaxhighlight lang="c">
 +
*FBx_MODE = (*FBx_MODE & 0xFF0FF8FC) | 0x100002;
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</syntaxhighlight>
 +
 +
 +
{{reg32|FB''x''_ADDR|addr=0x0C206110/0x0C207110|hifields=1|lofields=3|
 +
|16        |
 +
|W        |
 +
|ADDR      ||
 +
|8  |7|1  |
 +
|W  |U|W  |
 +
|ADDR| |UNK|
 +
}}
 +
{{regdesc
 +
|ADDR|High 24 bits of physical address for displayed framebuffer.
 +
|UNK |Unknown. Set during OSScreen initialisation.
 +
}}
 +
 +
{{reg32|FB''x''_WIDTH''x''|addr=0x0C206120/0x0C206198/0x0C207120/0x0C207198|hifields=1|lofields=2|
 +
|16  |
 +
|U  |
 +
|    ||
 +
|2|14|
 +
|U|W |
 +
| |PX|
 +
}}
 +
{{regdesc
 +
|PX|Target width of framebuffer in pixels.
 +
}}
 +
It's not known why there appears to be two of these registers for each framebuffer. OSScreen writes an identical value to each.
 +
 +
 +
{{reg32|FB''x''_ADDR_UPDATE|addr=0x0C206914/0x0C207914|hifields=1|lofields=1|
 +
|16    |
 +
|U    |
 +
|      ||
 +
|16    |
 +
|U    |
 +
|      |
 +
}}
 +
{{regdesc
 +
|FB''x''_ADDR_UPDATE|All bits cleared during OSScreen initialisation.
 +
}}
 +
This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_ADDR''' writes.
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/2530"