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Hardware/Espresso Registers (view source)
Revision as of 12:05, 25 January 2018
, 12:05, 25 January 2018Start reworking page with new GX2 research
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+==Register List==+{{reglist|Espresso Registers}}
−{{rld|0x0C206084|32|FB0_STATE|Controls TV framebuffer state.|drs=1}}
−{{rld|0x0C206100|32|FB0_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
−{{rld|0x0C206104|32|FB0_MODE|Controls TV framebuffer mode.|drs=1}}
−{{rld|0x0C206110|32|FB0_ADDR|Physical memory location of TV framebuffer.|drs=1}}
−{{rld|0x0C206120|32|FB0_WIDTH1|Width of TV framebuffer.|drs=2}}
−{{rld|0x0C206198|32|FB0_WIDTH2}}
−{{rld|0x0C206914|32|FB0_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
−{{rld|0x0C207084|32|FB1_STATE|Controls TV framebuffer state.|drs=1}}
−{{rld|0x0C207100|32|FB1_MODE_UPDATE|Update flag for TV framebuffer mode register.{{check}}|drs=1}}
−{{rld|0x0C207104|32|FB1_MODE|Controls TV framebuffer mode.|drs=1}}
−{{rld|0x0C207110|32|FB1_ADDR|Physical memory location of TV framebuffer.|drs=1}}
−{{rld|0x0C207120|32|FB1_WIDTH1|Width of TV framebuffer.|drs=2}}
−{{rld|0x0C207198|32|FB1_WIDTH2}}
−{{rld|0x0C207914|32|FB1_ADDR_UPDATE|Update flag for TV framebuffer.{{check}}|drs=1}}
−|}
−
−==Framebuffer Registers==
−{{reg32|FB''x''_STATE|addr=0x0C206084/0x0C207084|hifields=1|lofields=3|
−|16 |
−|U |
−| ||
−|7|1 |8|
−|U|RW |U|
−| |DSBL| |
−}}
−{{regdesc
−|DSBL|Set to ''disable'' the buffer, and clear to ''enable'' it.
−}}
−
−{{reg32|FB''x''_MODE_UPDATE|addr=0x0C206100/0x0C207100|hifields=1|lofields=2|
−|16 |
−|U |
−| ||
−|15|1 |
−|U |W |
−| |UPD|
−}}
−{{regdesc
−|UPD|Must be set directly after '''FB''x''_MODE''' changes.{{check}}
−}}
−This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_MODE''' writes.
+{{reg32|FB''x''_MODE|addr=0x0C206104/0x0C207104|hifields=3|lofields=4|+|8 |4 |4 |+|U |RW |U |+| |UNK1 | ||+|5|3 |6|2 |+|U|RW |U|RW |+| |UNK2| |UNK3|
−}}
−{{regdesc
−|UNK1|Unknown. Bit 20 (0x100000) set during OSScreen initialisation.
−|UNK2|Unknown. All bits cleared during OSScreen initialisation.
−|UNK3|Unknown. Bit 1 (0x2) set during OSScreen initialisation.
−A simplified view of how OSScreen sets up this register is as follows:
−<syntaxhighlight lang="c">
−*FBx_MODE = (*FBx_MODE & 0xFF0FF8FC) | 0x100002;
−</syntaxhighlight>
− +{{reg32|FB''x''_ADDR|addr=0x0C206110/0x0C207110|hifields=1|lofields=3|+|16 |
−|W |
−|ADDR ||
−|8 |7|1 |
−|W |U|W |
−|ADDR| |UNK|
−}}
−{{regdesc
−|ADDR|High 24 bits of physical address for displayed framebuffer.
−|UNK |Unknown. Set during OSScreen initialisation.
−}}
−
−{{reg32|FB''x''_WIDTH''x''|addr=0x0C206120/0x0C206198/0x0C207120/0x0C207198|hifields=1|lofields=2|
−|16 |
−|U |
−| ||
−|2|14|
−|U|W |
−| |PX|
−}}
−{{regdesc
−|PX|Target width of framebuffer in pixels.
−}}
−It's not known why there appears to be two of these registers for each framebuffer. OSScreen writes an identical value to each.
−
−
−{{reg32|FB''x''_ADDR_UPDATE|addr=0x0C206914/0x0C207914|hifields=1|lofields=1|
−|16 |
−|U |
−| ||
−|16 |
−|U |
−| |
−}}
−{{regdesc
−|FB''x''_ADDR_UPDATE|All bits cleared during OSScreen initialisation.
−}}
−This register is assumed to be an update flag{{check}} due to its proximity to '''FB''x''_ADDR''' writes.
Some of the Wii U's hardware components are available to and primarily used by the [[Hardware/Espresso|Espresso]]; including the [[GX2]], DSP and AX. These devices are mapped and available in [[Cafe OS]] userspace, used without the [[IOSU]]'s involvement.
+
+==GX2 Registers==
{{Infobox MMIO
{{Infobox MMIO
+| title = GX2 Registers
| arm = Full
| arm = Full
| ppc = Full
| ppc = Full
−| base = 0x0C000000
+| base = 0x0c200000
−| len = 0x400000
+| len = 0x30000
| bits = 32
| bits = 32
| ppcirq = ??
| ppcirq = ??
| latteirq = ??
| latteirq = ??
}}
}}
+''See Also: [[GX2]]''
−The GX2 consists of an R7xx family Radeon. While documentation perfectly matching the card is yet to be found, several documents can be brought together to form a reasonable picture of the register layout.
−Reverse-engineering has revealed that the GX2's MMIO registers (referred to as ''GpuF0MMReg'' in AMD's docs) are at 0x0c200000. The other MMIO locations (''GpuF0Pcie'', ''VGA_IO'') are not known at this point.
−*[https://developer.amd.com/wordpress/media/2012/10/42589_rv630_rrg_1.01o.pdf RV630 Register Reference Guide]
−:Register guide for a similar, but not identical, card. Covers 2D graphics, CRTCs, the memory controller, etc. Does ''not'' cover 3D. Addresses for registers starting with ''D1'' are known to match the GX2 - this reference has been successfully used to set up a framebuffer without Cafe OS running. There's evidence of another display not mentioned in this document - see the [[#Cafe OS|Cafe OS]] section below.
−*[http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/10/R6xx_3D_Registers.pdf Radeon R6xx/R7xx 3D Register Reference Guide]
−:3D register guide. Applies to the whole R7xx family, so there should be no differences for the GX2.{{check}} Has not been tried on hardware at time of writing.
−*[http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/10/R6xx_R7xx_3D.pdf Radeon R6xx/R7xx Acceleration]
−:Conceptual document explaining how to actually use the 3D engine, shader pipelines, caches, etc. Names registers, but does not give addresses (readers should cross-reference the 3D Register Reference Guide)
−}}
−====Cafe OS====
−Cafe OS applies various APIs on top of the GX2's raw hardware registers - [[gx2.rpl]] and [[Coreinit.rpl#Screen|OSScreen]]. OSScreen is the easier of the two to reverse-engineer, and reveals some unknowns in the hardware. For example, it uses the registers at ''GpuF0MMReg'':0x6100 to set up one framebuffer - which matches the D1GRPH registers according to the RV630 Register Reference Guide (see chapter 2.7.1 - Primary Display Graphics Control Registers). However, the API ''also'' uses registers at ''GpuF0MMReg'':0x7100 identically; suggesting the existence of another display controller at that location. The Register Reference Guide does not list any registers at that address, suggesting some major differences between the GX2 and the RV630.
−