102
edits
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ABIF stuff
Line 524:
Line 524:
}}
−'''device''' values:
−{{regdesc
−|0x0|CplCt (Center?)
−|0x1|CplTr (Top-right?)
−|0x2|CplTl (Top-left?)
−|0x3|CplBr (Bottom-right?)
−|0x4|CplBl (Bottom-left?)
−|0xC|[[Hardware/GX2|GPU]]
{{reg32 | LT_ABIF_ADDR | addr = 0x0d800620 | hifields = 3 | lofields = 1 |
{{reg32 | LT_ABIF_ADDR | addr = 0x0d800620 | hifields = 3 | lofields = 1 |
|2 |6 |8 |
|2 |6 |8 |
−|R/W |R/W |? |
+|R/W |R/W |R/W |
−|tile_id | device| ||
+|tile_id |device |offset ||
|16 |
|16 |
|R/W |
|R/W |
Line 532:
Line 532:
The ASIC bus interface register indexes a set of registers. The [[Hardware/GX2|GPU]] device seems to be the same as the registers at 0x0C200000 (ex: offset 0xF55C maps to 0x0C20F55C).
The ASIC bus interface register indexes a set of registers. The [[Hardware/GX2|GPU]] device seems to be the same as the registers at 0x0C200000 (ex: offset 0xF55C maps to 0x0C20F55C).
{{regdesc
{{regdesc
−|tile_id|Might only be applicable for device 0, CplCt
+|tile_id|See below
|device |See below
|device |See below
−|offset |Offset into registers, acccessed through LT_ABIF_DATA. Might be 24-bit?
+|offset |Offset into registers, acccessed through LT_ABIF_DATA.
−}}
}}
+'''tile_id'''/'''device''' values:
+{| class="wikitable"
+|-
+! Tile
+! Device
+! Description
+|-
+|0x0
+|0x0
+|CplCt (Center?)
+|-
+|0x0
+|0x1
+|CplTr (Top-right?)
+|-
+|0x0
+|0x2
+|CplTl (Top-left?)
+|-
+|0x0
+|0x3
+|CplBr (Bottom-right?)
+|-
+|0x0
+|0x4
+|CplBl (Bottom-left?)
+|-
+|0x2
+|0x0
+|MEM1 mirror (addresses are reordered: 0xC = offset 0x0)
+|-
+|0x2
+|0x1
+|MEM1 mirror (0x01000000)
+|-
+|0x2
+|0x2
+|? (0xDEADBEEF)
+|-
+|0x3
+|0x0
+|[[Hardware/GX2|GPU]]
+|}
{{hwstub}}
{{hwstub}}