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Line 207:
Line 207:
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
−{{rla|0x0d8005a4|32|LT_SYSCFG1|Debug mode flags}}
+{{rla|0x0d8005a4|32|LT_SYSCFG1|System configuration}}
{{rla|0x0d8005b0|32|LT_MEMCMPT|Memory compat mode for Wood}}
{{rla|0x0d8005b0|32|LT_MEMCMPT|Memory compat mode for Wood}}
{{rld|0x0d8005b4|32|LT_AHBCMPT|AHB compat mode for Wood}}
{{rld|0x0d8005b4|32|LT_AHBCMPT|AHB compat mode for Wood}}
Line 215:
Line 215:
{{rld|0x0d8005c8|32|LT_IOSTRCTRL2|I/O power strength control}}
{{rld|0x0d8005c8|32|LT_IOSTRCTRL2|I/O power strength control}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
−{{rld|0x0d8005e0|32|LT_RSTCTRL|Reset control}}
+{{rla|0x0d8005e0|32|LT_RSTCTRL0|Reset control}}
−{{rld|0x0d8005e4|32|LT_SYSCTRL|System control}}
+{{rla|0x0d8005e4|32|LT_RSTCTRL1|Reset control}}
{{rld|0x0d8005e8|32|LT_CLKGATE|Clock gating}}
{{rld|0x0d8005e8|32|LT_CLKGATE|Clock gating}}
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
Line 522:
Line 522:
}}
}}
−{{reg32 | LT_RSTCTRL | addr = 0x0d8005e0 | hifields = 1 | lofields = 3 |
+{{reg32 | LT_RSTCTRL0 | addr = 0x0d8005e0 | hifields = 1 | lofields = 3 |
|16 |
|16 |
|? |
|? |
Line 532:
Line 532:
{{regdesc
{{regdesc
|RTSB_AI_I2S5|AI I2S5 reset.
|RTSB_AI_I2S5|AI I2S5 reset.
+}}
+
+{{reg32 | LT_RSTCTRL1 | addr = 0x0d8005e4 | hifields = 1 | lofields = 5 |
+|16 |
+|? |
+| ||
+|7 |1 |1|1|6|
+|? |R/W|?|R/W|?|
+| |RTSB_DI2SATA| |RTSB_AHMN|
+}}
+{{regdesc
+|RTSB_DI2SATA|DI2SATA reset.
+|RTSB_AHMN|AHMN reset.
}}
}}