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Line 97:
Line 97:
{{rld|0x0d800174|32|HW_SPARE3|Unknown}}
{{rld|0x0d800174|32|HW_SPARE3|Unknown}}
{{rld|0x0d800180|32|HW_COMPAT|Drive interface resets}}
{{rld|0x0d800180|32|HW_COMPAT|Drive interface resets}}
−{{rld|0x0d800184|32|HW_RSTAHB|Memory resets}}
+{{rla|0x0d800184|32|HW_RSTAHB|Memory resets}}
{{rld|0x0d800188|32|HW_SPARE0|Unknown}}
{{rld|0x0d800188|32|HW_SPARE0|Unknown}}
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
{{rld|0x0d800190|32|HW_SYSCTRL|System control}}
{{rld|0x0d800190|32|HW_SYSCTRL|System control}}
−{{rld|0x0d800194|32|HW_RSTCTRL|Reset control}}
+{{rla|0x0d800194|32|HW_RSTCTRL|Reset control}}
{{rld|0x0d800198|32|HW_CLKGATE|Clock gating}}
{{rld|0x0d800198|32|HW_CLKGATE|Clock gating}}
{{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=16}}
{{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=16}}
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Line 213:
{{rld|0x0d8005bc|32|LT_IOP2X|Toggles the ARM clock multiplier}}
{{rld|0x0d8005bc|32|LT_IOP2X|Toggles the ARM clock multiplier}}
{{rld|0x0d8005c0|32|LT_EXICMPT|EXI compat mode for Wood}}
{{rld|0x0d8005c0|32|LT_EXICMPT|EXI compat mode for Wood}}
−{{rld|0x0d8005c8|32|LT_IOSTRCTRL2|I/O power strength control}}
+{{rld|0x0d8005c8|32|LT_IOSTRCTRL|I/O power strength control}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rla|0x0d8005e0|32|LT_RSTCTRL0|Reset control}}
{{rla|0x0d8005e0|32|LT_RSTCTRL0|Reset control}}
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Line 238:
== General Registers ==
== General Registers ==
+{{reg32 | HW_RSTAHB | addr = 0x0d800184 | hifields = 1 | lofields = 3 |
+|16 |
+|? |
+| ||
+|9 |1|6|
+|? |R/W|?|
+| |RSTB_AHM| |
+}}
+{{regdesc
+|RSTB_AHM|AHM reset.
+}}
+
{{reg32 | HW_SPARE1 | addr = 0x0d80018c | hifields = 1 | lofields = 5 |
{{reg32 | HW_SPARE1 | addr = 0x0d80018c | hifields = 1 | lofields = 5 |
|16 |
|16 |