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Hardware/Latte registers (view source)
Revision as of 21:42, 26 November 2023
, 21:42, 26 November 2023Use INTSTS and INTEN nomenclature where possible
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== Register list ==
== Register list ==
{{reglist|Latte Registers}}
{{reglist|Latte Registers}}
−{{rld|0x0d800000|32|HW_IPC_PPCMSG|[[Hardware/IPC|Wood IPC]]|drs=4}}
+{{rld|0x0d800000|32|HW_IPCPPCMSG|[[Hardware/IPC|Wood IPC]]|drs=4}}
−{{rld|0x0d800004|32|HW_IPC_PPCCTRL}}
+{{rld|0x0d800004|32|HW_IPCPPCCTRL}}
−{{rld|0x0d800008|32|HW_IPC_IOPMSG}}
+{{rld|0x0d800008|32|HW_IPCIOPMSG}}
−{{rld|0x0d80000c|32|HW_IPC_IOPCTRL}}
+{{rld|0x0d80000c|32|HW_IPCIOPCTRL}}
{{rld|0x0d800010|32|HW_TIMER|CPU timer|drs=2}}
{{rld|0x0d800010|32|HW_TIMER|CPU timer|drs=2}}
{{rld|0x0d800014|32|HW_ALARM}}
{{rld|0x0d800014|32|HW_ALARM}}
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{{rld|0x0d80001c|32|HW_VIDIM|VI dimmer}}
{{rld|0x0d80001c|32|HW_VIDIM|VI dimmer}}
{{rld|0x0d800024|32|HW_VISOLID|VI solid color}}
{{rld|0x0d800024|32|HW_VISOLID|VI solid color}}
−{{rld|0x0d800030|32|HW_PPCIRQFLAG|[[Hardware/Latte_IRQ_Controller|Wood IRQs]]|drs=5}}
+{{rld|0x0d800030|32|HW_PPCINTSTS|[[Hardware/Latte_IRQ_Controller|Wood IRQs]]|drs=5}}
−{{rld|0x0d800034|32|HW_PPCIRQMASK}}
+{{rld|0x0d800034|32|HW_PPCINTEN}}
−{{rld|0x0d800038|32|HW_IOPIRQFLAG}}
+{{rld|0x0d800038|32|HW_IOPINTSTS}}
−{{rld|0x0d80003c|32|HW_IOPIRQMASK}}
+{{rld|0x0d80003c|32|HW_IOPIRQINTEN}}
−{{rld|0x0d800040|32|HW_IOPFIQMASK}}
+{{rld|0x0d800040|32|HW_IOPFIQINTEN}}
{{rld|0x0d800044|32|HW_IOPINTPPC|Unknown}}
{{rld|0x0d800044|32|HW_IOPINTPPC|Unknown}}
{{rld|0x0d800048|32|HW_WDGINTSTS|AHB Watchdog interrupt status}}
{{rld|0x0d800048|32|HW_WDGINTSTS|AHB Watchdog interrupt status}}
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{{rld|0x0d800258|32|HW_AVE_I2C_INOUT_CTRL}}
{{rld|0x0d800258|32|HW_AVE_I2C_INOUT_CTRL}}
{{rld|0x0d80025c|32|HW_AVE_I2C_INOUT_SIZE}}
{{rld|0x0d80025c|32|HW_AVE_I2C_INOUT_SIZE}}
−{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
+{{rld|0x0d800400|32|LT_IPCPPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
−{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
+{{rld|0x0d800404|32|LT_IPCPPCCTRL0}}
−{{rld|0x0d800408|32|LT_IPC_IOPMSG0}}
+{{rld|0x0d800408|32|LT_IPCIOPMSG0}}
−{{rld|0x0d80040c|32|LT_IPC_IOPCTRL0}}
+{{rld|0x0d80040c|32|LT_IPCIOPCTRL0}}
−{{rld|0x0d800410|32|LT_IPC_PPCMSG1}}
+{{rld|0x0d800410|32|LT_IPCPPCMSG1}}
−{{rld|0x0d800414|32|LT_IPC_PPCCTRL1}}
+{{rld|0x0d800414|32|LT_IPCPPCCTRL1}}
−{{rld|0x0d800418|32|LT_IPC_IOPMSG1}}
+{{rld|0x0d800418|32|LT_IPCIOPMSG1}}
−{{rld|0x0d80041c|32|LT_IPC_IOPCTRL1}}
+{{rld|0x0d80041c|32|LT_IPCIOPCTRL1}}
−{{rld|0x0d800420|32|LT_IPC_PPCMSG2}}
+{{rld|0x0d800420|32|LT_IPCPPCMSG2}}
−{{rld|0x0d800424|32|LT_IPC_PPCCTRL2}}
+{{rld|0x0d800424|32|LT_IPCPPCCTRL2}}
−{{rld|0x0d800428|32|LT_IPC_IOPMSG2}}
+{{rld|0x0d800428|32|LT_IPCIOPMSG2}}
−{{rld|0x0d80042c|32|LT_IPC_IOPCTRL2}}
+{{rld|0x0d80042c|32|LT_IPCIOPCTRL2}}
−{{rld|0x0d800440|32|LT_PPCIRQFLAGALL0|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core)|drs=18}}
+{{rld|0x0d800440|32|LT_PPC0INTSTSALL|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core)|drs=18}}
−{{rld|0x0d800444|32|LT_PPCIRQFLAGLT0}}
+{{rld|0x0d800444|32|LT_PPC0INTSTSLT}}
−{{rld|0x0d800448|32|LT_PPCIRQMASKALL0}}
+{{rld|0x0d800448|32|LT_PPC0INTENALL}}
−{{rld|0x0d80044c|32|LT_PPCIRQMASKLT0}}
+{{rld|0x0d80044c|32|LT_PPC0INTENLT}}
−{{rld|0x0d800450|32|LT_PPCIRQFLAGALL1}}
+{{rld|0x0d800450|32|LT_PPC1INTSTSALL}}
−{{rld|0x0d800454|32|LT_PPCIRQFLAGLT1}}
+{{rld|0x0d800454|32|LT_PPC1INTSTSLT}}
−{{rld|0x0d800458|32|LT_PPCIRQMASKALL1}}
+{{rld|0x0d800458|32|LT_PPC1INTENALL}}
−{{rld|0x0d80045c|32|LT_PPCIRQMASKLT1}}
+{{rld|0x0d80045c|32|LT_PPC1INTENLT}}
−{{rld|0x0d800460|32|LT_PPCIRQFLAGALL2}}
+{{rld|0x0d800460|32|LT_PPC2INTSTSALL}}
−{{rld|0x0d800464|32|LT_PPCIRQFLAGLT2}}
+{{rld|0x0d800464|32|LT_PPC2INTSTSLT}}
−{{rld|0x0d800468|32|LT_PPCIRQMASKALL2}}
+{{rld|0x0d800468|32|LT_PPC2INTENALL}}
−{{rld|0x0d80046c|32|LT_PPCIRQMASKLT2}}
+{{rld|0x0d80046c|32|LT_PPC2INTENLT}}
−{{rld|0x0d800470|32|LT_IOPIRQFLAGALL}}
+{{rld|0x0d800470|32|LT_IOPINTSTSALL}}
−{{rld|0x0d800474|32|LT_IOPIRQFLAGLT}}
+{{rld|0x0d800474|32|LT_IOPINTSTSLT}}
−{{rld|0x0d800478|32|LT_IOPIRQMASKALL}}
+{{rld|0x0d800478|32|LT_IOPIRQINTENALL}}
−{{rld|0x0d80047c|32|LT_IOPIRQMASKLT}}
+{{rld|0x0d80047c|32|LT_IOPIRQINTENLT}}
−{{rld|0x0d800480|32|LT_IOPFIQMASKALL}}
+{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}
−{{rld|0x0d800484|32|LT_IOPFIQMASKLT}}
+{{rld|0x0d800484|32|LT_IOPFIQINTENLT}}
{{rld|0x0d8004a0|32|LT_WDG2INTSTS|AHB Watchdog interrupt status}}
{{rld|0x0d8004a0|32|LT_WDG2INTSTS|AHB Watchdog interrupt status}}
{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|AHB DMA transfer interrupt status}}
{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|AHB DMA transfer interrupt status}}