Changes

{{Infobox MMIO

{{Infobox MMIO

| arm = Full

| arm = Full

| base = 0x0d8b0800

| base = 0x0d8b0000

| len = 0x800

| len = 0x4000

| bits = 32

| bits = 32

| ppcirq = ???

| ppcirq = ???

}}

}}

Similarly to the [[Hardware/Memory_Controller|memory controller]] block connected to the AHB, the Latte hardware implements a customized XN (eXecute Never) controller to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>  

The AHM (AHB_MEM) was a custom bridge responsible for connecting the AHB bus to the [[Hardware/Memory Controller|Memory Controller]] in the old Hollywood's chipset.<br>

This controller is named AHMN (AHB memory XN?) by the IOSU.

The Latte hardware contains an enhanced version of this bridge dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>

 

Registers with the '''AHM_*''' prefix pertain to the old, base hardware block. Registers with the '''AHMN_*''' prefix pertain to the new, enhanced hardware block.  

== Register List ==

== Register List ==

{{reglist|XN Controller}}

{{reglist|AHMN Controller}}

{{rld|0x0d8b0800|32|AHMN_CFGMEM0|AHMN configuration for MEM0 protection}}

{{rld|0x0d8b0804|32|AHMN_CFGMEM1|AHMN configuration for MEM1 protection}}

{{rld|0x0d8b0808|32|AHMN_CFGMEM2|AHMN configuration for MEM2 protection}}

{{rld|0x0d8b080c|32|AHMN_RDBIMSK|AHMN read buffer invalidate mask}}

{{rld|0x0d8b0030|32|AHM_INTSTS|AHM interrupt status}}

{{rld|0x0d8b0800|32|AHMN_PROTMEM0|AHMN configuration for MEM0 protection}}

{{rld|0x0d8b0804|32|AHMN_PROTMEM1|AHMN configuration for MEM1 protection}}

{{rld|0x0d8b0808|32|AHMN_PROTMEM2|AHMN configuration for MEM2 protection}}

{{rld|0x0d8b080c|32|AHMN_RDBI|AHMN read buffer invalidate mask}}

{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}

{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}

{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}

{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN read/write transfer status}}

{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN transfer status}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}