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Hardware/Processor interface

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Revision as of 22:54, 20 August 2015 by Marionumber1 (talk | contribs) (Create basic Processor Interface page)
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Processor interface
Access
EspressoFull
StarbuckNone
Registers
Base0x0c000000
Length0xc0000
Access size32 bits
Byte orderBig Endian
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IRQ Sources

IRQ Description

Register List

IPC
Address Bits Name Description
0x0c000000 32 PI_INTSR_GLOBAL Globally-triggered IRQs
0x0c000004 32 PI_INTMR_GLOBAL Globally-allowed IRQs
0x0c000078 32 PI_INTSR_CPU0 Triggered IRQs for CPU0
0x0c00007c 32 PI_INTMR_CPU0 Allowed IRQs for CPU0
0x0c000080 32 PI_INTSR_CPU1 Triggered IRQs for CPU1
0x0c000084 32 PI_INTMR_CPU1 Allowed IRQs for CPU1
0x0c000088 32 PI_INTSR_CPU2 Triggered IRQs for CPU2
0x0c00008c 32 PI_INTMR_CPU2 Allowed IRQs for CPU2

Register Details

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