FBx_STATE (0x0C206084/0x0C207084)
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31
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30
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29
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28
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27
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26
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25
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24
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23
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22
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21
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20
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19
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18
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17
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16
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Access
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U
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Field
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
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U
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RW
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U
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Field
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DSBL
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Field
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Description
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DSBL
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Set to disable the buffer, and clear to enable it.
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FBx_MODE_UPDATE (0x0C206100/0x0C207100)
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31
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30
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29
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28
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27
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26
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25
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24
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23
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22
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21
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20
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19
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18
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17
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16
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Access
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U
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Field
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|
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
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U
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W
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Field
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UPD
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Field
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Description
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UPD
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Must be set directly after FBx_MODE changes.[check]
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This register is assumed to be an update flag[check] due to its proximity to FBx_MODE writes.
FBx_MODE (0x0C206104/0x0C207104)
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31
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30
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29
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28
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27
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26
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25
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24
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23
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22
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21
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20
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19
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18
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17
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16
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Access
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U
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RW
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U
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Field
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UNK1
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
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U
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RW
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U
|
RW
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Field
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UNK2
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UNK3
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Field
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Description
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UNK1
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Unknown. Bit 20 (0x100000) set during OSScreen initialisation.
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UNK2
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Unknown. All bits cleared during OSScreen initialisation.
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UNK3
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Unknown. Bit 1 (0x2) set during OSScreen initialisation.
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A simplified view of how OSScreen sets up this register is as follows:
*FBx_MODE = (*FBx_MODE & 0xFF0FF8FC) | 0x100002;
FBx_ADDR (0x0C206110/0x0C207110)
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|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
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20
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19
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18
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17
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16
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Access
|
W
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Field
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ADDR
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
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W
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U
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W
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Field
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ADDR
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UNK
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Field
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Description
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ADDR
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High 24 bits of physical address for displayed framebuffer.
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UNK
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Unknown. Set during OSScreen initialisation.
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FBx_WIDTHx (0x0C206120/0x0C206198/0x0C207120/0x0C207198)
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31
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30
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29
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28
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27
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26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
Access
|
U
|
Field
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
|
U
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W
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Field
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PX
|
Field
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Description
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PX
|
Target width of framebuffer in pixels.
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It's not known why there appears to be two of these registers for each framebuffer. OSScreen writes an identical value to each.
FBx_ADDR_UPDATE (0x0C206914/0x0C207914)
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31
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30
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29
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28
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27
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26
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25
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24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
Access
|
U
|
Field
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
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Access
|
U
|
Field
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Field
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Description
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FBx_ADDR_UPDATE
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All bits cleared during OSScreen initialisation.
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This register is assumed to be an update flag[check] due to its proximity to FBx_ADDR writes.