Register List
| Espresso Registers
|
| Address
|
Bits
|
Name
|
Description
|
| 0x0C206084
|
32
|
FB0_STATE
|
Controls TV framebuffer state.
|
| 0x0C206100
|
32
|
FB0_MODE_UPDATE
|
Update flag for TV framebuffer mode register.[check]
|
| 0x0C206104
|
32
|
FB0_MODE
|
Controls TV framebuffer mode.
|
| 0x0C206110
|
32
|
FB0_ADDR
|
Physical memory location of TV framebuffer.
|
| 0x0C206120
|
32
|
FB0_WIDTH1
|
Width of TV framebuffer.
|
| 0x0C206198
|
32
|
FB0_WIDTH2
|
| 0x0C206914
|
32
|
FB0_ADDR_UPDATE
|
Update flag for TV framebuffer.[check]
|
| 0x0C207084
|
32
|
FB1_STATE
|
Controls TV framebuffer state.
|
| 0x0C207100
|
32
|
FB1_MODE_UPDATE
|
Update flag for TV framebuffer mode register.[check]
|
| 0x0C207104
|
32
|
FB1_MODE
|
Controls TV framebuffer mode.
|
| 0x0C207110
|
32
|
FB1_ADDR
|
Physical memory location of TV framebuffer.
|
| 0x0C207120
|
32
|
FB1_WIDTH1
|
Width of TV framebuffer.
|
| 0x0C207198
|
32
|
FB1_WIDTH2
|
| 0x0C207914
|
32
|
FB1_ADDR_UPDATE
|
Update flag for TV framebuffer.[check]
|
Framebuffer Registers
| FBx_STATE (0x0C206084/0x0C207084)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
| Field
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
U
|
RW
|
U
|
| Field
|
|
DSBL
|
|
| Field
|
Description
|
| DSBL
|
Set to disable the buffer, and clear to enable it.
|
| FBx_MODE_UPDATE (0x0C206100/0x0C207100)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
| Field
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
U
|
W
|
| Field
|
|
UPD
|
| Field
|
Description
|
| UPD
|
Must be set directly after FBx_MODE changes.[check]
|
This register is assumed to be an update flag[check] due to its proximity to FBx_MODE writes.
| FBx_MODE (0x0C206104/0x0C207104)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
RW
|
U
|
| Field
|
|
UNK1
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
U
|
RW
|
U
|
RW
|
| Field
|
|
UNK2
|
|
UNK3
|
| Field
|
Description
|
| UNK1
|
Unknown. Bit 20 (0x100000) set during OSScreen initialisation.
|
| UNK2
|
Unknown. All bits cleared during OSScreen initialisation.
|
| UNK3
|
Unknown. Bit 1 (0x2) set during OSScreen initialisation.
|
A simplified view of how OSScreen sets up this register is as follows:
*FBx_MODE = (*FBx_MODE & 0xFF0FF8FC) | 0x100002;
| FBx_ADDR (0x0C206110/0x0C207110)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
W
|
| Field
|
ADDR
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
W
|
U
|
W
|
| Field
|
ADDR
|
|
UNK
|
| Field
|
Description
|
| ADDR
|
High 24 bits of physical address for displayed framebuffer.
|
| UNK
|
Unknown. Set during OSScreen initialisation.
|
| FBx_WIDTHx (0x0C206120/0x0C206198/0x0C207120/0x0C207198)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
| Field
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
U
|
W
|
| Field
|
|
PX
|
| Field
|
Description
|
| PX
|
Target width of framebuffer in pixels.
|
It's not known why there appears to be two of these registers for each framebuffer. OSScreen writes an identical value to each.
| FBx_ADDR_UPDATE (0x0C206914/0x0C207914)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
| Field
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
U
|
| Field
|
|
| Field
|
Description
|
| FBx_ADDR_UPDATE
|
All bits cleared during OSScreen initialisation.
|
This register is assumed to be an update flag[check] due to its proximity to FBx_ADDR writes.