Hardware/AHM controller

AHM controller
Access
Espresso	None
Starbuck	Full
Registers
Base	0x0d8b0800
Length	0x800
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???

Similarly to the memory controller block connected to the AHB, the Latte hardware implements a customized XN (eXecute Never) controller to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).
This controller is named AHMN (AHB memory XN?) by the IOSU.

Register List

XN Controller
Address	Bits	Name	Description
0x0d8b0800	32	AHMN_CFGMEM0	AHMN configuration for MEM0 protection
0x0d8b0804	32	AHMN_CFGMEM1	AHMN configuration for MEM1 protection
0x0d8b0808	32	AHMN_CFGMEM2	AHMN configuration for MEM2 protection
0x0d8b080c	32	AHMN_RDBIMSK	AHMN read buffer invalidate mask
0x0d8b0820	32	AHMN_INTMSK	AHMN interrupt mask
0x0d8b0824	32	AHMN_INTSTS	AHMN interrupt state
0x0d8b0840	32	AHMN_UNK	Unknown
0x0d8b0844	32	AHMN_UNK	Unknown
0x0d8b0850	32	AHMN_TRFSTS	AHMN read/write transfer state
0x0d8b0854	32	AHMN_WORKAROUND	Unknown
0x0d8b0900...0x0d8b0980	32	AHMN_MEM0	Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)
0x0d8b0a00...0x0d8b0c00	32	AHMN_MEM1	Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)
0x0d8b0c00...0x0d8b1000	32	AHMN_MEM2	Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)