Difference between revisions of "/dev/bsp/PPC"

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(Initial documentation for BSP's PPC entity)
 
(Add structure information for Summary and CoreProperties, other minor correctness tweaks)
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PPC is the [[:/dev/bsp]] entity responsible for managing the PowerPC cores in the [[Espresso]]. Depending on hardware version{{check}}, PPC either has one instance or three instances.
+
PPC is the [[:/dev/bsp]] entity responsible for managing the PowerPC cores in the [[Espresso]]. Depending on hardware version{{check}}, PPC either has one instance or three instances, one for each PowerPC core.
  
 
== Attributes ==
 
== Attributes ==
Line 89: Line 89:
 
| 16
 
| 16
 
| constant
 
| constant
| Returns a buffer filled with data calculated based on the hardware version at BSP init time. The data is identical between instances.
+
| Returns information about the PowerPC on this board, including the core count and bus speeds. The information returned is the same for all instances.
 
|}
 
|}
 +
<syntaxhighlight lang="C">
 +
typedef struct {
 +
    uint32_t systemClockFrequency;
 +
    uint32_t timerFrequency;
 +
} BSP_SYSTEM_CLOCK_INFO;
 +
typedef struct {
 +
    uint32_t numberOfCores;
 +
    uint32_t activeCoreBitmap; //bit 0/LSB = core 0, bit 1 = core 1, etc.
 +
    BSP_SYSTEM_CLOCK_INFO clock60x;
 +
} BSP_PPC_SUMMARY;
 +
 +
BSP_PPC_SUMMARY ppc;
 +
bspRead("PPC", 0, "Summary", sizeof(ppc), &ppc);
 +
 +
printf("powerpc has %d cores\n", ppc.numberOfCores);
 +
</syntaxhighlight>
  
 
=== CoreProperties ===
 
=== CoreProperties ===
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| 21
 
| 21
 
| constant
 
| constant
| Returns a buffer filled with data calculated based on the hardware version at BSP init time. The data is unique between instances.
+
| Returns information about the cache of a given PowerPC core.
 
|}
 
|}
 +
<syntaxhighlight lang="C">
 +
typedef struct {
 +
    uint32_t l2Size;
 +
    uint32_t l2LineSize;
 +
    uint32_t l2SectorSize;
 +
    uint32_t l2FetchSize;
 +
    uint32_t l2SetAssociativity;
 +
    uint8_t coreActive;
 +
} BSP_PPC_CORE_PROPERTIES;
 +
 +
BSP_PPC_CORE_PROPERTIES core1;
 +
bspRead("PPC", 1, "CoreProperties", sizeof(core1), &core1);
 +
 +
printf("core 1 l2 cache size: %x\n", core1.l2Size);
 +
</syntaxhighlight>
  
 
=== PVR ===
 
=== PVR ===
Line 121: Line 152:
 
| 4
 
| 4
 
|
 
|
| Reads out unknown properties from two [[:/dev/bsp/EE|EE]] instances and concatenates them.
+
| Reads out the PVR from {{hw|SEEPROM}} via [[:/dev/bsp/EE|EE]]. This is kept at offset 0x10 on Latte hardware, and 0x42 on Hollywood/Bollywood hardware.
 
|-
 
|-
 
| Write
 
| Write
 
| 4
 
| 4
 
|  
 
|  
| Sets [[:/dev/bsp/EE|EE]]'s first instance's control flag, then writes out the input value to two unknown EE instances.
+
| Sets [[:/dev/bsp/EE|EE]]'s first instance's control flag, then writes out the input value to 0x10 on Latte hardware, and 0x42 on Hollywood/Bollywood hardware.
 
|}
 
|}
  

Revision as of 09:50, 29 March 2020

PPC is the /dev/bsp entity responsible for managing the PowerPC cores in the Espresso. Depending on hardware version[check], PPC either has one instance or three instances, one for each PowerPC core.

Attributes

Exec

Availability: This attribute is only available on the first instance (index 0).

Permissions: BSP_PERMISSIONS_IOS_SUPV only.

Method Data Size Values
Write 1 1, 2 Writing a 1 calls the hardware-specific method to stop execution of the PowerPC, while writing 2 does the same to start it.
//start the PowerPC
int8_t start = 2;
bspWrite("PPC", 0, "Exec", 1, &start);
//stop the PowerPC
int8_t stop = 1;
bspWrite("PPC", 0, "Exec", 1, &stop);

Clock

Availability: This attribute is only available on the first instance (index 0).

Permissions: BSP_PERMISSIONS_IOS_SUPV only.

Method Data Size Values
Write 1 1 Writing a 1 tweaks the legacy clock registers, toggling FX and leaving the system in 162MHz/GameCube mode. Also toggles RTSB_DSKPLL, leaving it asserted.

EXIRegBoot

Availability: This attribute is only available on the first instance (index 0).

Permissions: BSP_PERMISSIONS_IOS_SUPV only.

Method Data Size Values
Write 48 see code Enables EXI, writes up to 16 32-bit instructions to the EXI boot stub[check] and sets PPCBOOT.
typedef struct {
    int32_t version; //offset 0x0; must equal 3
    uint32_t instructions[16]; //actual instruction data to copy; offset 0x4
    size_t size; //size of instructions in bytes. last two bits ignored. offset 0x44
} BSP_PPC_EXIRegBootArgs;

BSP_PPC_EXIRegBootArgs args = {
    .version = 3,
    .instructions = { 0x60000000, 0x48000000 },
    .size = 2 * sizeof(uint32_t),
};
bspWrite("PPC", 0, "EXIRegBoot", sizeof(args), args);

Summary

Availability: This attribute is available to all instances.

Permissions: BSP_PERMISSIONS_ALL.

Method Data Size Values
Query 16 constant Returns information about the PowerPC on this board, including the core count and bus speeds. The information returned is the same for all instances.
typedef struct {
    uint32_t systemClockFrequency;
    uint32_t timerFrequency;
} BSP_SYSTEM_CLOCK_INFO;
typedef struct {
    uint32_t numberOfCores;
    uint32_t activeCoreBitmap; //bit 0/LSB = core 0, bit 1 = core 1, etc.
    BSP_SYSTEM_CLOCK_INFO clock60x;
} BSP_PPC_SUMMARY;

BSP_PPC_SUMMARY ppc;
bspRead("PPC", 0, "Summary", sizeof(ppc), &ppc);

printf("powerpc has %d cores\n", ppc.numberOfCores);

CoreProperties

Availability: This attribute is available to all instances.

Permissions: BSP_PERMISSIONS_ALL.

Method Data Size Values
Query 21 constant Returns information about the cache of a given PowerPC core.
typedef struct {
    uint32_t l2Size;
    uint32_t l2LineSize;
    uint32_t l2SectorSize;
    uint32_t l2FetchSize;
    uint32_t l2SetAssociativity;
    uint8_t coreActive;
} BSP_PPC_CORE_PROPERTIES;

BSP_PPC_CORE_PROPERTIES core1;
bspRead("PPC", 1, "CoreProperties", sizeof(core1), &core1);

printf("core 1 l2 cache size: %x\n", core1.l2Size);

PVR

Availability: This attribute is only available on the first instance (index 0).

Permissions: BSP_PERMISSIONS_ALL.

Method Data Size Values
Read 4 Reads out the PVR from SEEPROM via EE. This is kept at offset 0x10 on Latte hardware, and 0x42 on Hollywood/Bollywood hardware.
Write 4 Sets EE's first instance's control flag, then writes out the input value to 0x10 on Latte hardware, and 0x42 on Hollywood/Bollywood hardware.

60XeDataStreaming

Availability: This attribute is only available on the first instance (index 0), and contains a hardware version check.

Permissions: BSP_PERMISSIONS_ALL.

Method Data Size Values
Read 1 0, 1 Returns a boolean value: 0 indicates that bit 3 (mask 0x8) in LT_60XE_CFG is set, while 1 indicates that bit is clear.
Write 1 0, 1 Sets bit 12 (mask 0x1000) in LT_60XE_CFG, which appears to be some kind of latch, sleeps, then sets bit 8 (when input is 0) or clears bit 8 (when input is 1).