Difference between revisions of "Hardware/Latte GPIOs"
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This register configures which pins can be controlled by the LT_GPIOE registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO registers, which are Starbuck-only. The LT_GPIO registers always have read access to all pins, but any writes (changes) must go through the
This register configures which pins can be controlled by the LT_GPIOE registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO registers, which are Starbuck-only. The LT_GPIO registers always have read access to all pins, but any writes (changes) must go through the registers if the corresponding bit is set in the LT_GPIO_OWNER register.
Revision as of 18:31, 2 July 2016
|Access size||32 bits|
|Byte order||Big Endian|
The Latte chipset includes at least 29 general purpose I/O lines with interrupt capability. Two sets of registers are provided, and the Espresso only has access to one set. This set accesses a configurable subset of the IO pins, which the Starbuck can select.
|0||IN||SYS_INT||Power button input (RTCSysInt, FanSpeed and/or ToucanSelect).|
|1||OUT||DWIFI_MODE||Unknown (DWiFiMode and/or SMCI2CClock).|
|2||OUT||FAN_PWR||Fan power, active high (FanPower and/or SMCI2CData).|
|3||OUT||DC_DC||DC/DC converter power (DCDCPwrCnt, DCDCPwrCnt2 and/or CCRIO3), active high.|
|4||OUT||AV_INT||A/V Encoder interrupt (AVInterrupt)?|
|5||OUT||ESP10_FIX||Unknown (ESP10WorkAround and/or CCRIO12).|
|6||OUT||AV_RST||A/V Encoder reset (AVReset)?|
|8||OUT||SDC_PWR||Unknown (SDC0S0Power and/or PADPD).|
|10||OUT||EEPROM_CS||SEEPROM Chip Select.|
|12||OUT||EEPROM_DO||Data to SEEPROM.|
|13||IN||EEPROM_DI||Data from SEEPROM.|
|14||OUT||AV0_I2C_CLOCK||A/V Encoder (#0) I²C Clock.|
|15||I/O||AV0_I2C_DATA||A/V Encoder (#0) I²C Data.|
|24||OUT||AV1_I2C_CLOCK||A/V Encoder (#1) I²C Clock.|
|25||I/O||AV1_I2C_DATA||A/V Encoder (#1) I²C Data.|
|30||OUT||UNKNOWN||Driven low before boot0 SD boot attempt.|
|0x0d8000c0||32||LT_GPIOE_OUT||GPIO Outputs (Espresso access)|
|0x0d8000c4||32||LT_GPIOE_DIR||GPIO Direction (Espresso access)|
|0x0d8000c8||32||LT_GPIOE_IN||GPIO Inputs (Espresso access)|
|0x0d8000cc||32||LT_GPIOE_INTLVL||GPIO Interrupt Levels (Espresso access)|
|0x0d8000d0||32||LT_GPIOE_INTFLAG||GPIO Interrupt Flags (Espresso access)|
|0x0d8000d4||32||LT_GPIOE_INTMASK||GPIO Interrupt Masks (Espresso access)|
|0x0d8000d8||32||LT_GPIOE_INMIR||GPIO Input Mirror (Espresso access)|
|0x0d8000dc||32||LT_GPIO_ENABLE||GPIO Enable (Starbuck only)|
|0x0d8000e0||32||LT_GPIO_OUT||GPIO Outputs (Starbuck only)|
|0x0d8000e4||32||LT_GPIO_DIR||GPIO Direction (Starbuck only)|
|0x0d8000e8||32||LT_GPIO_IN||GPIO Inputs (Starbuck only)|
|0x0d8000ec||32||LT_GPIO_INTLVL||GPIO Interrupt Levels (Starbuck only)|
|0x0d8000f0||32||LT_GPIO_INTFLAG||GPIO Interrupt Flags (Starbuck only)|
|0x0d8000f4||32||LT_GPIO_INTMASK||GPIO Interrupt Masks (Starbuck only)|
|0x0d8000f8||32||LT_GPIO_INMIR||GPIO Input Mirror (Starbuck only)|
|0x0d8000fc||32||LT_GPIO_OWNER||GPIO Owner Select (Starbuck only)|
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
This register can be read to obtain the current input value of the GPIO pins.
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the LT_GPIO_INTLVL register, then the corresponding bit in LT_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in LT_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
Only the bits set in this register propagate their interrupts to the master Latte GPIO interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in LT_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is LT_GPIO_INTMASK & LT_GPIO_INTFLAG & ~LT_GPIO_OWNER.
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. [check]
This register configures which pins can be controlled by the LT_GPIOE registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO registers, which are Starbuck-only. The LT_GPIO registers always have read access to all pins, but any writes (changes) must go through the LT_GPIOE registers if the corresponding bit is set in the LT_GPIO_OWNER register.
These registers operate identically to their LT_GPIO counterparts above, but they only control the pins which have their respective LT_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the Latte GPIOE interrupt (#10). The generation logic would be LT_GPIOE_INTFLAG & LT_GPIOE_INTMASK, with an implicit AND with LT_GPIO_OWNER since the GPIOE registers are already masked with the LT_GPIO_OWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.