Hardware/Latte GPIOs
The Latte chipset includes two groups of general purpose I/O lines with interrupt capability. Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
| Latte GPIOs | |
| Latte Registers | |
| Access | |
|---|---|
| Espresso | Partial |
| Starbuck | Full |
| Registers | |
| Base | 0x0d8000c0, 0x0d800520 |
| Length | 0x80 |
| Access size | 32 bits |
| Byte order | Big Endian |
| IRQs | |
| Espresso | None |
| Latte | 10,11 |
Pin connections
| Bit | Group | Direction | Connection | Description |
|---|---|---|---|---|
| 0 | 1 | IN | RTCSysInt | Power button input. |
| 0 | 2 | OUT | FanSpeed | Fan speed. |
| 0 | 1 | I/O | ToucanSelect | "Toucan" select (devkit only). |
| 1 | 1 | OUT | DWiFiMode | DWiFi mode. |
| 1 | 2 | IN | SMCI2CClock | SMC (surface mounted components) I²C Clock. |
| 2 | 1 | OUT | FanPower | Fan power, active high. |
| 2 | 2 | IN | SMCI2CData | SMC (surface mounted components) I²C Data. |
| 3 | 1 | OUT | DCDCPwrCnt | DC/DC converter power (group 1), active high. |
| 3 | 2 | OUT | DCDCPwrCnt2 | DC/DC converter power (group 2), active high. |
| 3 | 1 | OUT | CCRIO3 | Unknown (duplicate?) |
| 4 | 1 | UNK | UNKNOWN | Unknown. |
| 4 | 2 | IN | AVInterrupt | A/V encoder interrupt (from Espresso). |
| 5 | 1 | OUT | ESP10WorkAround | Unknown. |
| 5 | 2 | OUT | CCRIO12 | Unknown. |
| 6 | 1 | UNK | UNKNOWN | Unknown. |
| 6 | 2 | OUT | AVReset | A/V encoder reset (from Espresso). |
| 7 | 1 | UNK | UNKNOWN | Unknown. |
| 8 | 1 | OUT | PADPD | Gamepad power state. |
| 9 | 1 | UNK | UNKNOWN | Unknown. |
| 10 | 1 | OUT | EEPROM_CS | SEEPROM Chip Select. |
| 11 | 1 | OUT | EEPROM_SK | SEEPROM Clock. |
| 12 | 1 | OUT | EEPROM_DO | Data to SEEPROM. |
| 13 | 1 | IN | EEPROM_DI | Data from SEEPROM. |
| 14 | 1 | OUT | AV0I2CClock | A/V Encoder (#0) I²C Clock. |
| 15 | 1 | OUT | AV0I2CData | A/V Encoder (#0) I²C Data. |
| 16 | 1 | I/O | NDEV_LED | Development unit's LED (devkit only). |
| 16 | 1 | OUT | DEBUG0 | Debug Testpoint. |
| 17 | 1 | OUT | DEBUG1 | Debug Testpoint. |
| 18 | 1 | OUT | DEBUG2 | Debug Testpoint. |
| 19 | 1 | OUT | DEBUG3 | Debug Testpoint. |
| 20 | 1 | OUT | DEBUG4 | Debug Testpoint. |
| 21 | 1 | OUT | DEBUG5 | Debug Testpoint. |
| 22 | 1 | OUT | DEBUG6 | Debug Testpoint. |
| 23 | 1 | OUT | DEBUG7 | Debug Testpoint. |
| 24 | 1 | OUT | AV1I2CClock | A/V Encoder (#1) I²C Clock. |
| 25 | 1 | OUT | AV1I2CData | A/V Encoder (#1) I²C Data. |
| 26 | 1 | OUT | MuteLamp | Unknown. |
| 27 | 1 | OUT | BlueToothMode | BlueTooth mode. |
| 28 | 1 | OUT | CCRHReset | CCR (constant current regulator?) hard reset. |
| 29 | 1 | OUT | WiFiMode | WiFi mode. |
| 30 | 1 | OUT | SDC0S0Power | SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card. |
Register list
| Latte GPIOs (group 1) | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d8000c0 | 32 | LT_GPIOE_OUT | GPIO Outputs (Espresso access) |
| 0x0d8000c4 | 32 | LT_GPIOE_DIR | GPIO Direction (Espresso access) |
| 0x0d8000c8 | 32 | LT_GPIOE_IN | GPIO Inputs (Espresso access) |
| 0x0d8000cc | 32 | LT_GPIOE_INTLVL | GPIO Interrupt Levels (Espresso access) |
| 0x0d8000d0 | 32 | LT_GPIOE_INTFLAG | GPIO Interrupt Flags (Espresso access) |
| 0x0d8000d4 | 32 | LT_GPIOE_INTMASK | GPIO Interrupt Masks (Espresso access) |
| 0x0d8000d8 | 32 | LT_GPIOE_INMIR | GPIO Input Mirror (Espresso access) |
| 0x0d8000dc | 32 | LT_GPIO_ENABLE | GPIO Enable (Starbuck only) |
| 0x0d8000e0 | 32 | LT_GPIO_OUT | GPIO Outputs (Starbuck only) |
| 0x0d8000e4 | 32 | LT_GPIO_DIR | GPIO Direction (Starbuck only) |
| 0x0d8000e8 | 32 | LT_GPIO_IN | GPIO Inputs (Starbuck only) |
| 0x0d8000ec | 32 | LT_GPIO_INTLVL | GPIO Interrupt Levels (Starbuck only) |
| 0x0d8000f0 | 32 | LT_GPIO_INTFLAG | GPIO Interrupt Flags (Starbuck only) |
| 0x0d8000f4 | 32 | LT_GPIO_INTMASK | GPIO Interrupt Masks (Starbuck only) |
| 0x0d8000f8 | 32 | LT_GPIO_INMIR | GPIO Input Mirror (Starbuck only) |
| 0x0d8000fc | 32 | LT_GPIO_OWNER | GPIO Owner Select (Starbuck only) |
| Latte GPIOs (group 2) | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800520 | 32 | LT_GPIO2E_OUT | GPIO Outputs (Espresso access) |
| 0x0d800524 | 32 | LT_GPIOE2_DIR | GPIO Direction (Espresso access) |
| 0x0d800528 | 32 | LT_GPIOE2_IN | GPIO Inputs (Espresso access) |
| 0x0d80052c | 32 | LT_GPIOE2_INTLVL | GPIO Interrupt Levels (Espresso access) |
| 0x0d800530 | 32 | LT_GPIOE2_INTFLAG | GPIO Interrupt Flags (Espresso access) |
| 0x0d800534 | 32 | LT_GPIOE2_INTMASK | GPIO Interrupt Masks (Espresso access) |
| 0x0d800538 | 32 | LT_GPIOE2_INMIR | GPIO Input Mirror (Espresso access) |
| 0x0d80053c | 32 | LT_GPIO2_ENABLE | GPIO Enable (Starbuck only) |
| 0x0d800540 | 32 | LT_GPIO2_OUT | GPIO Outputs (Starbuck only) |
| 0x0d800544 | 32 | LT_GPIO2_DIR | GPIO Direction (Starbuck only) |
| 0x0d800548 | 32 | LT_GPIO2_IN | GPIO Inputs (Starbuck only) |
| 0x0d80054c | 32 | LT_GPIO2_INTLVL | GPIO Interrupt Levels (Starbuck only) |
| 0x0d800550 | 32 | LT_GPIO2_INTFLAG | GPIO Interrupt Flags (Starbuck only) |
| 0x0d800554 | 32 | LT_GPIO2_INTMASK | GPIO Interrupt Masks (Starbuck only) |
| 0x0d800558 | 32 | LT_GPIO2_INMIR | GPIO Input Mirror (Starbuck only) |
| 0x0d80055c | 32 | LT_GPIO2_OWNER | GPIO Owner Select (Starbuck only) |
Register descriptions
| LT_GPIO_ENABLE (0x0d8000dc) | ||
| 3124 | 230 | |
| Access | U | R/W |
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
| LT_GPIO_OUT (0x0d8000e0) | ||
| 3124 | 230 | |
| Access | U | R/W |
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
| LT_GPIO_DIR (0x0d8000e4) | ||
| 3124 | 230 | |
| Access | U | R/W |
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
| LT_GPIO_IN (0x0d8000e8) | ||
| 3124 | 230 | |
| Access | U | R |
This register can be read to obtain the current input value of the GPIO pins.
| LT_GPIO_INTLVL (0x0d8000ec) | ||
| 3124 | 230 | |
| Access | U | R/W |
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
| LT_GPIO_INTFLAG (0x0d8000f0) | ||
| 3124 | 230 | |
| Access | U | R/Z |
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the LT_GPIO_INTLVL register, then the corresponding bit in LT_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in LT_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
| LT_GPIO_INTMASK (0x0d8000f4) | ||
| 3124 | 230 | |
| Access | U | R/W |
Only the bits set in this register propagate their interrupts to the master Latte GPIO interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in LT_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is LT_GPIO_INTMASK & LT_GPIO_INTFLAG & ~LT_GPIO_OWNER.
| LT_GPIO_INMIR (0x0d8000f8) | ||
| 3124 | 230 | |
| Access | U | R |
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. [check]
| LT_GPIO_OWNER (0x0d8000fc) | ||
| 3124 | 230 | |
| Access | U | R/W |
This register configures which pins can be controlled by the LT_GPIOE registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO registers, which are Starbuck-only. The LT_GPIO registers always have read access to all pins, but any writes (changes) must go through the LT_GPIOE registers if the corresponding bit is set in the LT_GPIO_OWNER register.
| LT_GPIOE_OUT (0x0d8000c0) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE_DIR (0x0d8000c4) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE_IN (0x0d8000c8) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOE_INTLVL (0x0d8000cc) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE_INTFLAG (0x0d8000d0) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| LT_GPIOE_INTMASK (0x0d8000d4) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE_INMIR (0x0d8000d8) | ||
| 3124 | 230 | |
| Access | U | R |
These registers operate identically to their LT_GPIO counterparts above, but they only control the pins which have their respective LT_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the Latte GPIOE interrupt (#10). The generation logic would be LT_GPIOE_INTFLAG & LT_GPIOE_INTMASK, with an implicit AND with LT_GPIO_OWNER since the GPIOE registers are already masked with the LT_GPIO_OWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.
| LT_GPIO2_ENABLE (0x0d80053c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIO2_OUT (0x0d800540) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIO2_DIR (0x0d800544) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIO2_IN (0x0d800548) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIO2_INTLVL (0x0d80054c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIO2_INTFLAG (0x0d800550) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| LT_GPIO2_INTMASK (0x0d800554) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIO2_INMIR (0x0d800558) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIO2_OWNER (0x0d80055c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE2_OUT (0x0d800520) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE2_DIR (0x0d800524) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE2_IN (0x0d800528) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOE2_INTLVL (0x0d80052c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE2_INTFLAG (0x0d800530) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| LT_GPIOE2_INTMASK (0x0d800534) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOE2_INMIR (0x0d800538) | ||
| 3124 | 230 | |
| Access | U | R |
These registers are identical to those used for the first GPIO group.