Difference between revisions of "Hardware/Latte IRQ Controller"

From WiiUBrew
Jump to navigation Jump to search
Line 3: Line 3:
 
| arm = Full
 
| arm = Full
 
| base = 0x0d800030, 0x0d800440
 
| base = 0x0d800030, 0x0d800440
| len = 0x10, 0x48
+
| len = 0x14, 0x48
 
| bits = 32
 
| bits = 32
 
}}
 
}}
Line 121: Line 121:
 
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
 
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
 
|}
 
|}
 +
 +
== Register descriptions ==
 +
{{regsimple|LT_INTSR_AHBALL_PPCx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
 +
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 +
----
 +
{{regsimple|LT_INTSR_AHBLT_PPCx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
 +
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 +
----
 +
{{regsimple|LT_INTMR_AHBALL_PPCx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
 +
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 +
----
 +
{{regsimple|LT_INTMR_AHBLT_PPCx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
 +
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 +
----
 +
{{regsimple|LT_INTSR_AHBALL_ARM|addr=0x0d800470|bits=32|access=R/Z}}
 +
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 +
----
 +
{{regsimple|LT_INTSR_AHBLT_ARM|addr=0x0d800474|bits=32|access=R/Z}}
 +
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 +
----
 +
{{regsimple|LT_INTMR_AHBALL_ARM|addr=0x0d800478|bits=32|access=R/W}}
 +
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
 +
----
 +
{{regsimple|LT_INTMR_AHBLT_ARM|addr=0x0d80047c|bits=32|access=R/W}}
 +
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.

Revision as of 19:18, 14 April 2016

Latte IRQ Controller
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800030, 0x0d800440
Length0x14, 0x48
Access size32 bits
Byte orderBig Endian
This box: view  talk  edit

IRQ Sources

IRQ Description
0 Starbuck Timer
1 NAND Interface
2 AES Engine
3 SHA-1 Engine
4 USB Host Controller (EHCI)
5 USB Host Controller (OHCI0)
6 USB Host Controller (OHCI1)
7 SD Host Controller
8 802.11 Wireless
9 Unknown
10 Latte GPIOs (Espresso)
11 Latte GPIOs (Starbuck)
12 Unknown
13 Undefined
14 Undefined
15 Undefined
16 Undefined
17 Power button (reset)
18 Drive Interface (DI)
19 Undefined
20 Unknown
21 Undefined
22 Undefined
23 Undefined
24 Undefined
25 Undefined
26 Undefined
27 Undefined
28 Unknown
29 Undefined
30 IPC (Espresso)
31 IPC (Starbuck)

Register List

The Latte IRQ engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores and the ARM core. Each core's region of the SMP block has registers equivalent to the old global block.

Compat block

Global compat block
Address Bits Name Description
0x0d800030 32 LT_INTSR_PPC_COMPAT Triggered IRQs for the PPC in vWii
0x0d800034 32 LT_INTMR_PPC_COMPAT Allowed IRQs for the PPC in vWii
0x0d800038 32 LT_INTSR_ARM_COMPAT Triggered IRQs for the ARM in vWii
0x0d80003c 32 LT_INTMR_ARM_COMPAT Allowed IRQs for the ARM in vWii
0x0d800040 32 LT_INTMR_ARM2x_COMPAT Unknown

SMP block

SMP block - PPC core 0
Address Bits Name Description
0x0d800440 32 LT_INTSR_AHBALL_PPC0 Triggered AHB IRQs for PPC core 0 (all)
0x0d800444 32 LT_INTSR_AHBLT_PPC0 Triggered AHB IRQs for PPC core 0 (Latte only)
0x0d800448 32 LT_INTMR_AHBALL_PPC0 Allowed AHB IRQs for PPC core 0 (all)
0x0d80044c 32 LT_INTMR_AHBLT_PPC0 Allowed AHB IRQs for PPC core 0 (Latte only)
SMP block - PPC core 1
Address Bits Name Description
0x0d800450 32 LT_INTSR_AHBALL_PPC1 Triggered AHB IRQs for PPC core 1 (all)
0x0d800454 32 LT_INTSR_AHBLT_PPC1 Triggered AHB IRQs for PPC core 1 (Latte only)
0x0d800458 32 LT_INTMR_AHBALL_PPC1 Allowed AHB IRQs for PPC core 1 (all)
0x0d80045c 32 LT_INTMR_AHBLT_PPC1 Allowed AHB IRQs for PPC core 1 (Latte only)
SMP block - PPC core 2
Address Bits Name Description
0x0d800460 32 LT_INTSR_AHBALL_PPC2 Triggered AHB IRQs for PPC core 2 (all)
0x0d800464 32 LT_INTSR_AHBLT_PPC2 Triggered AHB IRQs for PPC core 2 (Latte only)
0x0d800468 32 LT_INTMR_AHBALL_PPC2 Allowed AHB IRQs for PPC core 2 (all)
0x0d80046c 32 LT_INTMR_AHBLT_PPC2 Allowed AHB IRQs for PPC core 2 (Latte only)
SMP block - ARM core
Address Bits Name Description
0x0d800470 32 LT_INTSR_AHBALL_ARM Triggered AHB IRQs for ARM core (all)
0x0d800474 32 LT_INTSR_AHBLT_ARM Triggered AHB IRQs for ARM core (Latte only)
0x0d800478 32 LT_INTMR_AHBALL_ARM Allowed AHB IRQs for ARM core (all)
0x0d80047c 32 LT_INTMR_AHBLT_ARM Allowed AHB IRQs for ARM core (Latte only)
0x0d800480 32 LT_INTMR_AHBALL_ARM2x Unknown (all)
0x0d800484 32 LT_INTMR_AHBLT_ARM2x Unknown (Latte only)

Register descriptions

LT_INTSR_AHBALL_PPCx (0x0d800440/0x0d800450/0x0d800460)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.


LT_INTSR_AHBLT_PPCx (0x0d800444/0x0d800454/0x0d800464)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.


LT_INTMR_AHBALL_PPCx (0x0d800448/0x0d800458/0x0d800468)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.


LT_INTMR_AHBLT_PPCx (0x0d80044c/0x0d80045c/0x0d80046c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.


LT_INTSR_AHBALL_ARM (0x0d800470)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.


LT_INTSR_AHBLT_ARM (0x0d800474)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.


LT_INTMR_AHBALL_ARM (0x0d800478)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.


LT_INTMR_AHBLT_ARM (0x0d80047c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.