Difference between revisions of "Hardware/Latte IRQ Controller"

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The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
 
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
IOSU distinguishes interrupt sources that also existed in the Hollywood chipset (AHBALL) and new sources that are exclusive to the Latte (AHBLT).
+
IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LT).
Additionally, the (emulated) Hollywood IRQ registers are still available for compat mode (vWii) and debugging.
 
  
==IRQ Sources==
+
== IRQ Sources ==
 
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 
|- style="background-color: #ddd;"
 
|- style="background-color: #ddd;"
 
! IRQ
 
! IRQ
! Type
+
! Group
 
! Description
 
! Description
 
|-
 
|-
| (1 << 0) || AHBALL || Timer (Starbuck)
+
| 0 || ALL || Timer (Starbuck)
 
|-
 
|-
| (1 << 1) || AHBALL || {{hw|NAND Interface}}
+
| 1 || ALL || {{hw|NAND Interface}}
 
|-
 
|-
| (1 << 2) || AHBALL || {{hw|AES Engine}}
+
| 2 || ALL || {{hw|AES Engine}}
 
|-
 
|-
| (1 << 3) || AHBALL || {{hw|SHA-1 Engine}}
+
| 3 || ALL || {{hw|SHA-1 Engine}}
 
|-
 
|-
| (1 << 4) || AHBALL || {{hw|USB Host Controller}} (EHCI-0)
+
| 4 || ALL || {{hw|USB Host Controller}} (EHCI-0)
 
|-
 
|-
| (1 << 5) || AHBALL || {{hw|USB Host Controller}} (OHCI-0:0)
+
| 5 || ALL || {{hw|USB Host Controller}} (OHCI-0:0)
 
|-
 
|-
| (1 << 6) || AHBALL || {{hw|USB Host Controller}} (OHCI-0:1)
+
| 6 || ALL || {{hw|USB Host Controller}} (OHCI-0:1)
 
|-
 
|-
| (1 << 7) || AHBALL || {{hw|SD Host Controller}}
+
| 7 || ALL || {{hw|SD Host Controller}}
 
|-
 
|-
| (1 << 8) || AHBALL || {{hw|802.11 Wireless}}
+
| 8 || ALL || {{hw|802.11 Wireless}}
 
|-
 
|-
| (1 << 9) || AHBALL || Undefined
+
| 9 || ALL || Undefined
 
|-
 
|-
| (1 << 10) || AHBALL || {{hw|Latte GPIOs}} (Espresso)
+
| 10 || ALL || {{hw|Latte GPIOs}} (Espresso)
 
|-
 
|-
| (1 << 11) || AHBALL || {{hw|Latte GPIOs}} (Starbuck)
+
| 11 || ALL || {{hw|Latte GPIOs}} (Starbuck)
 
|-
 
|-
| (1 << 12) || AHBALL || SYSPROT
+
| 12 || ALL || SYSPROT
 
|-
 
|-
| (1 << 13) || AHBALL || Undefined
+
| 13 || ALL || Undefined
 
|-
 
|-
| (1 << 14) || AHBALL || Undefined
+
| 14 || ALL || Undefined
 
|-
 
|-
| (1 << 15) || AHBALL || Undefined
+
| 15 || ALL || Undefined
 
|-
 
|-
| (1 << 16) || AHBALL || Undefined
+
| 16 || ALL || {{hw|USB Host Controller}} (EHCI-1)
 
|-
 
|-
| (1 << 17) || AHBALL || Power button
+
| 17 || ALL || Power button
 
|-
 
|-
| (1 << 18) || AHBALL || Drive Interface
+
| 18 || ALL || Drive Interface
 
|-
 
|-
| (1 << 19) || AHBALL || {{hw|USB Host Controller}} (EHCI-1)
+
| 19 || ALL || Undefined
 
|-
 
|-
| (1 << 20) || AHBALL || EXI RTC
+
| 20 || ALL || EXI RTC
 
|-
 
|-
| (1 << 21) || AHBALL || Undefined
+
| 21 || ALL || Undefined
 
|-
 
|-
| (1 << 22) || AHBALL || Undefined
+
| 22 || ALL || Undefined
 
|-
 
|-
| (1 << 23) || AHBALL || Undefined
+
| 23 || ALL || Undefined
 
|-
 
|-
| (1 << 24) || AHBALL || Undefined
+
| 24 || ALL || Undefined
 
|-
 
|-
| (1 << 25) || AHBALL || Undefined
+
| 25 || ALL || Undefined
 
|-
 
|-
| (1 << 26) || AHBALL || Undefined
+
| 26 || ALL || Undefined
 
|-
 
|-
| (1 << 27) || AHBALL || Undefined
+
| 27 || ALL || Undefined
 
|-
 
|-
| (1 << 28) || AHBALL || SATA
+
| 28 || ALL || SATA
 
|-
 
|-
| (1 << 29) || AHBALL || Undefined
+
| 29 || ALL || Undefined
 
|-
 
|-
| (1 << 30) || AHBALL || {{hw|IPC}} (Espresso compat)
+
| 30 || ALL || {{hw|IPC}} (Espresso compat)
 
|-
 
|-
| (1 << 31) || AHBALL || {{hw|IPC}} (Starbuck compat)
+
| 31 || ALL || {{hw|IPC}} (Starbuck compat)
 
|-
 
|-
| (1 << 0) || AHBLT || {{hw|SD Host Controller}}
+
| 0 || LT || {{hw|SD Host Controller}}
 
|-
 
|-
| (1 << 1) || AHBLT || Unknown
+
| 1 || LT || Unknown
 
|-
 
|-
| (1 << 2) || AHBLT || Unknown
+
| 2 || LT || Unknown
 
|-
 
|-
| (1 << 3) || AHBLT || Unknown
+
| 3 || LT || {{hw|USB Host Controller}} (OHCI-1:0)
 
|-
 
|-
| (1 << 4) || AHBLT || DRH
+
| 4 || LT || {{hw|USB Host Controller}} (EHCI-2)
 
|-
 
|-
| (1 << 5) || AHBLT || Unknown
+
| 5 || LT || {{hw|USB Host Controller}} (OHCI-2:0)
 
|-
 
|-
| (1 << 6) || AHBLT || Unknown
+
| 6 || LT || Unknown
 
|-
 
|-
| (1 << 7) || AHBLT || Unknown
+
| 7 || LT || Unknown
 
|-
 
|-
| (1 << 8) || AHBLT || {{hw|AES Engine}} (AESS)
+
| 8 || LT || {{hw|AES Engine}} (AESS)
 
|-
 
|-
| (1 << 9) || AHBLT || {{hw|SHA-1 Engine}} (SHAS-1)
+
| 9 || LT || {{hw|SHA-1 Engine}} (SHAS-1)
 
|-
 
|-
| (1 << 10) || AHBLT || Unknown
+
| 10 || LT || Unknown
 
|-
 
|-
| (1 << 11) || AHBLT || Unknown
+
| 11 || LT || Unknown
 
|-
 
|-
| (1 << 12) || AHBLT || Unknown
+
| 12 || LT || Unknown
 
|-
 
|-
| (1 << 13) || AHBLT || I2C (Espresso)
+
| 13 || LT || I2C (Espresso)
 
|-
 
|-
| (1 << 14) || AHBLT || I2C (Starbuck)
+
| 14 || LT || I2C (Starbuck)
 
|-
 
|-
| (1 << 15) || AHBLT || Undefined
+
| 15 || LT || Undefined
 
|-
 
|-
| (1 << 16) || AHBLT || Undefined
+
| 16 || LT || Undefined
 
|-
 
|-
| (1 << 17) || AHBLT || Undefined
+
| 17 || LT || Undefined
 
|-
 
|-
| (1 << 18) || AHBLT || Undefined
+
| 18 || LT || Undefined
 
|-
 
|-
| (1 << 19) || AHBLT || Undefined
+
| 19 || LT || Undefined
 
|-
 
|-
| (1 << 20) || AHBLT || Undefined
+
| 20 || LT || Undefined
 
|-
 
|-
| (1 << 21) || AHBLT || Undefined
+
| 21 || LT || Undefined
 
|-
 
|-
| (1 << 22) || AHBLT || Undefined
+
| 22 || LT || Undefined
 
|-
 
|-
| (1 << 23) || AHBLT || Undefined
+
| 23 || LT || Undefined
 
|-
 
|-
| (1 << 24) || AHBLT || Undefined
+
| 24 || LT || Undefined
 
|-
 
|-
| (1 << 25) || AHBLT || Undefined
+
| 25 || LT || Undefined
 
|-
 
|-
| (1 << 26) || AHBLT || {{hw|IPC}} (Espresso CPU2)
+
| 26 || LT || {{hw|IPC}} (Espresso CPU2)
 
|-
 
|-
| (1 << 27) || AHBLT || {{hw|IPC}} (Starbuck CPU2)
+
| 27 || LT || {{hw|IPC}} (Starbuck CPU2)
 
|-
 
|-
| (1 << 28) || AHBLT || {{hw|IPC}} (Espresso CPU1)
+
| 28 || LT || {{hw|IPC}} (Espresso CPU1)
 
|-
 
|-
| (1 << 29) || AHBLT || {{hw|IPC}} (Starbuck CPU1)
+
| 29 || LT || {{hw|IPC}} (Starbuck CPU1)
 
|-
 
|-
| (1 << 30) || AHBLT || {{hw|IPC}} (Espresso CPU0)
+
| 30 || LT || {{hw|IPC}} (Espresso CPU0)
 
|-
 
|-
| (1 << 31) || AHBLT || {{hw|IPC}} (Starbuck CPU0)
+
| 31 || LT || {{hw|IPC}} (Starbuck CPU0)
 
|-
 
|-
 
|}
 
|}
  
==Register List==
+
== Register List ==
Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for compat mode (vWii) and another for normal mode (Wii U).
+
Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware.
The subset used for normal mode is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
+
The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
There are also traces of additional unused registers which appear to have been used in the past for debugging purposes (ARM2x).
 
  
===Compat block===
+
=== Wood block ===
{{reglist|Global compat block}}
+
{{reglist|Wood block}}
{{rla|0x0d800030|32|LT_INTSR_PPC_COMPAT|Triggered IRQs for the PPC in vWii}}
+
{{rla|0x0d800030|32|HW_PPCIRQFLAG|Triggered IRQs for the PPC core in vWii}}
{{rla|0x0d800034|32|LT_INTMR_PPC_COMPAT|Allowed IRQs for the PPC in vWii}}
+
{{rla|0x0d800034|32|HW_PPCIRQMASK|Allowed IRQs for the PPC core in vWii}}
{{rla|0x0d800038|32|LT_INTSR_ARM_COMPAT|Triggered IRQs for the ARM in vWii}}
+
{{rla|0x0d800038|32|HW_ARMIRQFLAG|Triggered IRQs for the ARM core in vWii}}
{{rla|0x0d80003c|32|LT_INTMR_ARM_COMPAT|Allowed IRQs for the ARM in vWii}}
+
{{rla|0x0d80003c|32|HW_ARMIRQMASK|Allowed IRQs for the ARM core in vWii}}
{{rld|0x0d800040|32|LT_INTMR_ARM2x_COMPAT|Unknown}}
+
{{rld|0x0d800040|32|HW_ARMFIQMASK|Allowed FIQs for the ARM core in vWii}}
 
|}
 
|}
  
===SMP block===
+
=== Latte block ===
{{reglist|SMP block - PPC core 0}}
+
{{reglist|Latte block - PPC core 0}}
{{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800440|32|LT_PPCIRQFLAGALL0|Triggered IRQs for PPC core 0 (all)}}
{{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d800444|32|LT_PPCIRQFLAGLT0|Triggered IRQs for PPC core 0 (Latte only)}}
{{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800448|32|LT_PPCIRQMASKALL0|Allowed IRQs for PPC core 0 (all)}}
{{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d80044c|32|LT_PPCIRQMASKLT0|Allowed IRQs for PPC core 0 (Latte only)}}
 
|}
 
|}
  
{{reglist|SMP block - PPC core 1}}
+
{{reglist|Latte block - PPC core 1}}
{{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800450|32|LT_PPCIRQFLAGALL1|Triggered IRQs for PPC core 1 (all)}}
{{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d800454|32|LT_PPCIRQFLAGLT1|Triggered IRQs for PPC core 1 (Latte only)}}
{{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800458|32|LT_PPCIRQMASKALL1|Allowed IRQs for PPC core 1 (all)}}
{{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d80045c|32|LT_PPCIRQMASKLT1|Allowed IRQs for PPC core 1 (Latte only)}}
 
|}
 
|}
  
{{reglist|SMP block - PPC core 2}}
+
{{reglist|Latte block - PPC core 2}}
{{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800460|32|LT_PPCIRQFLAGALL2|Triggered IRQs for PPC core 2 (all)}}
{{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d800464|32|LT_PPCIRQFLAGLT2|Triggered IRQs for PPC core 2 (Latte only)}}
{{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800468|32|LT_PPCIRQMASKALL2|Allowed IRQs for PPC core 2 (all)}}
{{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d80046c|32|LT_PPCIRQMASKLT2|Allowed IRQs for PPC core 2 (Latte only)}}
 
|}
 
|}
  
{{reglist|SMP block - ARM core}}
+
{{reglist|Latte block - ARM core}}
{{rla|0x0d800470|32|LT_INTSR_AHBALL_ARM|Triggered AHB IRQs for ARM core (all)}}
+
{{rla|0x0d800470|32|LT_ARMIRQFLAGALL|Triggered IRQs for ARM core (all)}}
{{rla|0x0d800474|32|LT_INTSR_AHBLT_ARM|Triggered AHB IRQs for ARM core (Latte only)}}
+
{{rla|0x0d800474|32|LT_ARMIRQFLAGLT|Triggered IRQs for ARM core (Latte only)}}
{{rla|0x0d800478|32|LT_INTMR_AHBALL_ARM|Allowed AHB IRQs for ARM core (all)}}
+
{{rla|0x0d800478|32|LT_ARMIRQMASKALL|Allowed IRQs for ARM core (all)}}
{{rla|0x0d80047c|32|LT_INTMR_AHBLT_ARM|Allowed AHB IRQs for ARM core (Latte only)}}
+
{{rla|0x0d80047c|32|LT_ARMIRQMASKLT|Allowed IRQs for ARM core (Latte only)}}
{{rld|0x0d800480|32|LT_INTMR_AHBALL_ARM2x|Unknown (all)}}
+
{{rld|0x0d800480|32|LT_ARMFIQMASKALL|Allowed FIQs for the ARM core (all)}}
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
+
{{rld|0x0d800484|32|LT_ARMFIQMASKLT|Allowed FIQs for the ARM core (Latte only)}}
 
|}
 
|}
  
 
== Register descriptions ==
 
== Register descriptions ==
{{regsimple|LT_INTSR_AHBALL_PPCx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCIRQFLAGALLx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
{{regsimple|LT_INTSR_AHBLT_PPCx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCIRQFLAGLTx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
{{regsimple|LT_INTMR_AHBALL_PPCx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+
{{regsimple|LT_PPCIRQMASKALLx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
{{regsimple|LT_INTMR_AHBLT_PPCx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+
{{regsimple|LT_PPCIRQMASKLTx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
{{regsimple|LT_INTSR_AHBALL_ARM|addr=0x0d800470|bits=32|access=R/Z}}
+
{{regsimple|LT_ARMIRQFLAGALL|addr=0x0d800470|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
{{regsimple|LT_INTSR_AHBLT_ARM|addr=0x0d800474|bits=32|access=R/Z}}
+
{{regsimple|LT_ARMIRQFLAGLT|addr=0x0d800474|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
{{regsimple|LT_INTMR_AHBALL_ARM|addr=0x0d800478|bits=32|access=R/W}}
+
{{regsimple|LT_ARMIRQMASKALL|addr=0x0d800478|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
 
----
 
----
{{regsimple|LT_INTMR_AHBLT_ARM|addr=0x0d80047c|bits=32|access=R/W}}
+
{{regsimple|LT_ARMIRQMASKLT|addr=0x0d80047c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.

Latest revision as of 21:00, 19 November 2019

Latte IRQ Controller
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800030, 0x0d800440
Length0x14, 0x48
Access size32 bits
Byte orderBig Endian
This box: view  talk  edit

The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both. IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LT).

IRQ Sources

IRQ Group Description
0 ALL Timer (Starbuck)
1 ALL NAND Interface
2 ALL AES Engine
3 ALL SHA-1 Engine
4 ALL USB Host Controller (EHCI-0)
5 ALL USB Host Controller (OHCI-0:0)
6 ALL USB Host Controller (OHCI-0:1)
7 ALL SD Host Controller
8 ALL 802.11 Wireless
9 ALL Undefined
10 ALL Latte GPIOs (Espresso)
11 ALL Latte GPIOs (Starbuck)
12 ALL SYSPROT
13 ALL Undefined
14 ALL Undefined
15 ALL Undefined
16 ALL USB Host Controller (EHCI-1)
17 ALL Power button
18 ALL Drive Interface
19 ALL Undefined
20 ALL EXI RTC
21 ALL Undefined
22 ALL Undefined
23 ALL Undefined
24 ALL Undefined
25 ALL Undefined
26 ALL Undefined
27 ALL Undefined
28 ALL SATA
29 ALL Undefined
30 ALL IPC (Espresso compat)
31 ALL IPC (Starbuck compat)
0 LT SD Host Controller
1 LT Unknown
2 LT Unknown
3 LT USB Host Controller (OHCI-1:0)
4 LT USB Host Controller (EHCI-2)
5 LT USB Host Controller (OHCI-2:0)
6 LT Unknown
7 LT Unknown
8 LT AES Engine (AESS)
9 LT SHA-1 Engine (SHAS-1)
10 LT Unknown
11 LT Unknown
12 LT Unknown
13 LT I2C (Espresso)
14 LT I2C (Starbuck)
15 LT Undefined
16 LT Undefined
17 LT Undefined
18 LT Undefined
19 LT Undefined
20 LT Undefined
21 LT Undefined
22 LT Undefined
23 LT Undefined
24 LT Undefined
25 LT Undefined
26 LT IPC (Espresso CPU2)
27 LT IPC (Starbuck CPU2)
28 LT IPC (Espresso CPU1)
29 LT IPC (Starbuck CPU1)
30 LT IPC (Espresso CPU0)
31 LT IPC (Starbuck CPU0)

Register List

Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware. The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.

Wood block

Wood block
Address Bits Name Description
0x0d800030 32 HW_PPCIRQFLAG Triggered IRQs for the PPC core in vWii
0x0d800034 32 HW_PPCIRQMASK Allowed IRQs for the PPC core in vWii
0x0d800038 32 HW_ARMIRQFLAG Triggered IRQs for the ARM core in vWii
0x0d80003c 32 HW_ARMIRQMASK Allowed IRQs for the ARM core in vWii
0x0d800040 32 HW_ARMFIQMASK Allowed FIQs for the ARM core in vWii

Latte block

Latte block - PPC core 0
Address Bits Name Description
0x0d800440 32 LT_PPCIRQFLAGALL0 Triggered IRQs for PPC core 0 (all)
0x0d800444 32 LT_PPCIRQFLAGLT0 Triggered IRQs for PPC core 0 (Latte only)
0x0d800448 32 LT_PPCIRQMASKALL0 Allowed IRQs for PPC core 0 (all)
0x0d80044c 32 LT_PPCIRQMASKLT0 Allowed IRQs for PPC core 0 (Latte only)
Latte block - PPC core 1
Address Bits Name Description
0x0d800450 32 LT_PPCIRQFLAGALL1 Triggered IRQs for PPC core 1 (all)
0x0d800454 32 LT_PPCIRQFLAGLT1 Triggered IRQs for PPC core 1 (Latte only)
0x0d800458 32 LT_PPCIRQMASKALL1 Allowed IRQs for PPC core 1 (all)
0x0d80045c 32 LT_PPCIRQMASKLT1 Allowed IRQs for PPC core 1 (Latte only)
Latte block - PPC core 2
Address Bits Name Description
0x0d800460 32 LT_PPCIRQFLAGALL2 Triggered IRQs for PPC core 2 (all)
0x0d800464 32 LT_PPCIRQFLAGLT2 Triggered IRQs for PPC core 2 (Latte only)
0x0d800468 32 LT_PPCIRQMASKALL2 Allowed IRQs for PPC core 2 (all)
0x0d80046c 32 LT_PPCIRQMASKLT2 Allowed IRQs for PPC core 2 (Latte only)
Latte block - ARM core
Address Bits Name Description
0x0d800470 32 LT_ARMIRQFLAGALL Triggered IRQs for ARM core (all)
0x0d800474 32 LT_ARMIRQFLAGLT Triggered IRQs for ARM core (Latte only)
0x0d800478 32 LT_ARMIRQMASKALL Allowed IRQs for ARM core (all)
0x0d80047c 32 LT_ARMIRQMASKLT Allowed IRQs for ARM core (Latte only)
0x0d800480 32 LT_ARMFIQMASKALL Allowed FIQs for the ARM core (all)
0x0d800484 32 LT_ARMFIQMASKLT Allowed FIQs for the ARM core (Latte only)

Register descriptions

LT_PPCIRQFLAGALLx (0x0d800440/0x0d800450/0x0d800460)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.


LT_PPCIRQFLAGLTx (0x0d800444/0x0d800454/0x0d800464)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.


LT_PPCIRQMASKALLx (0x0d800448/0x0d800458/0x0d800468)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.


LT_PPCIRQMASKLTx (0x0d80044c/0x0d80045c/0x0d80046c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.


LT_ARMIRQFLAGALL (0x0d800470)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.


LT_ARMIRQFLAGLT (0x0d800474)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.


LT_ARMIRQMASKALL (0x0d800478)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.


LT_ARMIRQMASKLT (0x0d80047c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.