Difference between revisions of "Hardware/Latte Registers"

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(Initial fields listing for HW_IOPWRCTRL)
(Add AV I²C registers, rename existing registers to "SMC_I2C")
 
Line 37: Line 37:
 
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
{{rld|0x0d800068|32|UNKNOWN|Unknown}}
+
<!-- check: are these really Latte-only? -->
{{rld|0x0d80006c|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=2}}
 +
{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
 
{{rld|0x0d800070|32|HW_AIP_PROT|[[Hardware/EXI|EXI]] access control}}
 
{{rld|0x0d800070|32|HW_AIP_PROT|[[Hardware/EXI|EXI]] access control}}
 
{{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}}
 
{{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}}
Line 121: Line 122:
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
+
<!-- check: are these really Latte-only? -->
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=4}}
{{rld|0x0d800258|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
 +
{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
 +
{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
 
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
Line 184: Line 187:
 
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
{{rld|0x0d800570|32|LT_I2C_CLOCK|I2C related|drs=6}}
+
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK|[[Hardware/Latte I²C|Latte I²C]] (SMC)|drs=6}}
{{rld|0x0d800574|32|LT_I2C_INOUT_DATA}}
+
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
{{rld|0x0d800578|32|LT_I2C_INOUT_CTRL}}
+
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
{{rld|0x0d80057c|32|LT_I2C_INOUT_SIZE}}
+
{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
{{rld|0x0d800580|32|LT_I2C_INT_MASK}}
+
{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
{{rld|0x0d800584|32|LT_I2C_INT_STATE}}
+
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
 
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|Debug mode flags}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|Debug mode flags}}

Latest revision as of 08:11, 27 February 2020

Latte Registers
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800000
Length???
Access size32 bits
Byte orderBig Endian
IRQs
Espresso12
Latte0,10,11,17,30,31,...[check]
This box: view  talk  edit

The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the Espresso. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

Registers with the HW_* prefix are used both by Wood (Hollywood/Bollywood) and Latte hardware. Registers with the LT_* prefix are exclusive to Latte hardware.

Register list

Latte Registers
Address Bits Name Description
0x0d800000 32 HW_IPC_PPCMSG Wood IPC
0x0d800004 32 HW_IPC_PPCCTRL
0x0d800008 32 HW_IPC_ARMMSG
0x0d80000c 32 HW_IPC_ARMCTRL
0x0d800010 32 HW_TIMER CPU timer
0x0d800014 32 HW_ALARM
0x0d800018 32 HW_VI1CFG VI configuration
0x0d80001c 32 HW_VIDIM VI dimmer
0x0d800024 32 HW_VISOLID VI solid color
0x0d800030 32 HW_PPCIRQFLAG Wood IRQs
0x0d800034 32 HW_PPCIRQMASK
0x0d800038 32 HW_ARMIRQFLAG
0x0d80003c 32 HW_ARMIRQMASK
0x0d800040 32 HW_ARMFIQMASK
0x0d800044 32 HW_IOPINTPPC Unknown
0x0d800048 32 HW_WDGINTSTS AHB Watchdog interrupt status
0x0d80004c 32 HW_WDGCFG AHB Watchdog configuration
0x0d800050 32 HW_DMAADRINTSTS AHB DMA transfer interrupt status
0x0d800054 32 HW_CPUADRINTSTS AHB CPU transfer interrupt status
0x0d800058 32 HW_DBGINTSTS Debug interrupt status
0x0d80005c 32 HW_DBGINTEN Debug interrupt enable
0x0d800060 32 HW_SRNPROT SRAM access control
0x0d800064 32 HW_BUSPROT AHB access control
0x0d800068 32 LT_AVE_I2C_INT_MASK[check] Latte I²C (AV encoder)
0x0d80006c 32 LT_AVE_I2C_INT_STATE
0x0d800070 32 HW_AIP_PROT EXI access control
0x0d800074 32 HW_AIP_IOCTRL Unknown
0x0d800080 32 HW_USBDBG0 USB related
0x0d800084 32 HW_USBDBG1
0x0d800088 32 HW_USBFRCRST
0x0d80008c 32 HW_USBIOTEST
0x0d800090 32 HW_ELA_REG_ADDR CoreSight ELA
0x0d800094 32 HW_ELA_REG_DATA
0x0d800098 32 HW_MEMTSTN
0x0d80009c 32 HW_MEMTSTP
0x0d8000c0 32 HW_GPIOB_OUT Wood GPIOs
0x0d8000c4 32 HW_GPIOB_DIR
0x0d8000c8 32 HW_GPIOB_IN
0x0d8000cc 32 HW_GPIOB_INTLVL
0x0d8000d0 32 HW_GPIOB_INTFLAG
0x0d8000d4 32 HW_GPIOB_INTMASK
0x0d8000d8 32 HW_GPIOB_STRAPS
0x0d8000dc 32 HW_GPIO_ENABLE
0x0d8000e0 32 HW_GPIO_OUT
0x0d8000e4 32 HW_GPIO_DIR
0x0d8000e8 32 HW_GPIO_IN
0x0d8000ec 32 HW_GPIO_INTLVL
0x0d8000f0 32 HW_GPIO_INTFLAG
0x0d8000f4 32 HW_GPIO_INTMASK
0x0d8000f8 32 HW_GPIO_STRAPS
0x0d8000fc 32 HW_GPIO_OWNER
0x0d800100 32 HW_ARB_CFG_M0 AHB arbiter configuration
0x0d800104 32 HW_ARB_CFG_M1
0x0d800108 32 HW_ARB_CFG_M2
0x0d80010c 32 HW_ARB_CFG_M3
0x0d800110 32 HW_ARB_CFG_M4
0x0d800114 32 HW_ARB_CFG_M5
0x0d800118 32 HW_ARB_CFG_M6
0x0d80011c 32 HW_ARB_CFG_M7
0x0d800120 32 HW_ARB_CFG_M8
0x0d800124 32 HW_ARB_CFG_M9
0x0d800128 32 HW_ARB_CFG_MA
0x0d80012c 32 HW_ARB_CFG_MB
0x0d800130 32 HW_ARB_CFG_MC
0x0d800134 32 HW_ARB_CFG_MD
0x0d800138 32 HW_ARB_CFG_ME
0x0d80013c 32 HW_ARB_CFG_MF
0x0d800140 32 HW_ARB_CFG_CPU
0x0d800144 32 HW_ARB_CFG_DMA
0x0d800148 32 HW_ARB_PCNTCFG
0x0d80014c 32 HW_ARB_PCNTSTS
0x0d800180 32 HW_DIRSTB Drive interface resets
0x0d800184 32 HW_MEMRSTB Memory resets
0x0d800188 32 HW_SPARE0 Unknown
0x0d80018c 32 HW_SPARE1 Maps boot0 and controls a few other things
0x0d800190 32 HW_CLOCKS Clock information
0x0d800194 32 HW_RSTB System resets
0x0d800198 32 HW_IFPWRCTRL Interface power control
0x0d80019c 32 HW_PLLDR PLL registers
0x0d8001a8 32 UNKNOWN
0x0d8001b0 32 HW_PLLSYS
0x0d8001b4 32 HW_PLLSYSEXT
0x0d8001b8 32 HW_PLLDSK
0x0d8001bc 32 HW_PLLDDR
0x0d8001c0 32 HW_PLLDDREXT
0x0d8001c4 32 HW_PLLVI
0x0d8001c8 32 HW_PLLVIEXT
0x0d8001cc 32 HW_PLLAI
0x0d8001d0 32 HW_PLLAIEXT
0x0d8001d4 32 HW_PLLUSB
0x0d8001d8 32 HW_PLLUSBEXT
0x0d8001dc 32 HW_IOPWRCTRL I/O power control
0x0d8001e0 32 HW_IOSTRCTRL0 I/O power strength control
0x0d8001e4 32 HW_IOSTRCTRL1 I/O power strength control
0x0d8001e8 32 HW_CLKSTRCTRL Clock power strength control
0x0d8001ec 32 HW_OTPCMD OTP
0x0d8001f0 32 HW_OTPDATA
0x0d8001f4 32 HW_DBGCLK External debugger
0x0d8001f8 32 HW_OBSCLKOCTRL
0x0d8001fc 32 HW_OBSCLKICTRL
0x0d800200 32 HW_DBGPORT
0x0d800204 32 HW_SICLKDIV SI related
0x0d800208 32 HW_SICTRL
0x0d80020c 32 HW_SIDATA
0x0d800210 32 HW_SIINT
0x0d800214 32 HW_CHIPREVID Hardware version (Wood)
0x0d800224 32 UNKNOWN Unknown
0x0d800250 32 LT_AVE_I2C_CLOCK[check] Latte I²C (AV encoder)
0x0d800254 32 LT_AVE_I2C_INOUT_DATA
0x0d800258 32 LT_AVE_I2C_INOUT_CTRL
0x0d80025c 32 LT_AVE_I2C_INOUT_SIZE
0x0d800400 32 LT_IPC_PPCMSG0 Latte IPC (per-core)
0x0d800404 32 LT_IPC_PPCCTRL0
0x0d800408 32 LT_IPC_ARMMSG0
0x0d80040c 32 LT_IPC_ARMCTRL0
0x0d800410 32 LT_IPC_PPCMSG1
0x0d800414 32 LT_IPC_PPCCTRL1
0x0d800418 32 LT_IPC_ARMMSG1
0x0d80041c 32 LT_IPC_ARMCTRL1
0x0d800420 32 LT_IPC_PPCMSG2
0x0d800424 32 LT_IPC_PPCCTRL2
0x0d800428 32 LT_IPC_ARMMSG2
0x0d80042c 32 LT_IPC_ARMCTRL2
0x0d800440 32 LT_PPCIRQFLAGALL0 Latte IRQs (per-core)
0x0d800444 32 LT_PPCIRQFLAGLT0
0x0d800448 32 LT_PPCIRQMASKALL0
0x0d80044c 32 LT_PPCIRQMASKLT0
0x0d800450 32 LT_PPCIRQFLAGALL1
0x0d800454 32 LT_PPCIRQFLAGLT1
0x0d800458 32 LT_PPCIRQMASKALL1
0x0d80045c 32 LT_PPCIRQMASKLT1
0x0d800460 32 LT_PPCIRQFLAGALL2
0x0d800464 32 LT_PPCIRQFLAGLT2
0x0d800468 32 LT_PPCIRQMASKALL2
0x0d80046c 32 LT_PPCIRQMASKLT2
0x0d800470 32 LT_ARMIRQFLAGALL
0x0d800474 32 LT_ARMIRQFLAGLT
0x0d800478 32 LT_ARMIRQMASKALL
0x0d80047c 32 LT_ARMIRQMASKLT
0x0d800480 32 LT_ARMFIQMASKALL
0x0d800484 32 LT_ARMFIQMASKLT
0x0d8004a0 32 LT_WDG2INTSTS AHB Watchdog interrupt status
0x0d8004a4 32 LT_DMAADR2INTSTS AHB DMA transfer interrupt status
0x0d8004a8 32 LT_CPUADR2INTSTS AHB CPU transfer interrupt status
0x0d8004c8 32 UNKNOWN Unknown
0x0d8004cc 32 UNKNOWN Unknown
0x0d8004d0 32 UNKNOWN Unknown
0x0d8004d4 32 UNKNOWN Unknown
0x0d8004dc 32 UNKNOWN Unknown
0x0d8004e0 32 UNKNOWN Unknown
0x0d8004e4 32 UNKNOWN Unknown
0x0d800500 32 UNKNOWN Unknown
0x0d800504 32 UNKNOWN Unknown
0x0d800510 32 LT_OTPPROT Bitmask used to lock out chunks of OTP (0x20 bytes each)
0x0d800514 32 LT_SYSPROT Hardware sandbox for Wood
0x0d800520 32 LT_GPIOB_OUT Latte GPIOs
0x0d800524 32 LT_GPIOB_DIR
0x0d800528 32 LT_GPIOB_IN
0x0d80052c 32 LT_GPIOB_INTLVL
0x0d800530 32 LT_GPIOB_INTFLAG
0x0d800534 32 LT_GPIOB_INTMASK
0x0d800538 32 LT_GPIOB_STRAPS
0x0d80053c 32 LT_GPIO_ENABLE
0x0d800540 32 LT_GPIO_OUT
0x0d800544 32 LT_GPIO_DIR
0x0d800548 32 LT_GPIO_IN
0x0d80054c 32 LT_GPIO_INTLVL
0x0d800550 32 LT_GPIO_INTFLAG
0x0d800554 32 LT_GPIO_INTMASK
0x0d800558 32 LT_GPIO_STRAPS
0x0d80055c 32 LT_GPIO_OWNER
0x0d800570 32 LT_SMC_I2C_CLOCK Latte I²C (SMC)
0x0d800574 32 LT_SMC_I2C_INOUT_DATA
0x0d800578 32 LT_SMC_I2C_INOUT_CTRL
0x0d80057c 32 LT_SMC_I2C_INOUT_SIZE
0x0d800580 32 LT_SMC_I2C_INT_MASK
0x0d800584 32 LT_SMC_I2C_INT_STATE
0x0d8005a0 32 LT_CHIPREVID Hardware version (Latte)
0x0d8005a4 32 LT_DEBUG Debug mode flags
0x0d8005b0 32 LT_MEMCMPT Memory compat mode for Wood
0x0d8005b4 32 LT_AHBCMPT AHB compat mode for Wood
0x0d8005b8 32 LT_AICMPT AI compat mode for Wood
0x0d8005bc 32 LT_IOP2X Toggles the ARM clock multiplier
0x0d8005c0 32 LT_EXICMPT EXI compat mode for Wood
0x0d8005c8 32 LT_IOSTRCTRL2 I/O power strength control
0x0d8005cc 32 UNKNOWN Unknown
0x0d8005e0 32 LT_RSTB System resets
0x0d8005e4 32 LT_MEMRSTB Memory resets
0x0d8005e8 32 LT_IFPWRCTRL Interface power control
0x0d8005ec 32 LT_PLLSYS System PLL configuration
0x0d800620 32 LT_ABIF_CPLTL_ADDR ASIC bus interface
0x0d800624 32 LT_ABIF_CPLTL_DATA
0x0d800628 32 UNKNOWN Unknown
0x0d800640 32 LT_60XE_CFG 60Xe data bus configuration
0x0d800660 32 UNKNOWN Unknown
0x0d800664 32 UNKNOWN Unknown
0x0d800708 32 LT_DCCMPT DC compat mode for Wood

General Registers

HW_CHIPREVID (0x0d800214)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R R
Field VERHI VERLO

This register contains the hardware revision of the Wood chipset (used for vWii mode). The IOSU also stores this value in a flag inside it's kernel's heap.
Hardware revision -> IOSU equivalent flag -> BSP hardware version
0x?? -> 0x00000000 -> BSP_HARDWARE_VERSION_UNKNOWN
0x00 -> 0x00000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_1
0x10 -> 0x10000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_2
0x?? -> 0x10100001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_PROD_FOR_WII
0x11 -> 0x10100008 -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO
0x?? -> 0x1010000C -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO_ESPRESSO
0x20 -> 0x20000001 -> BSP_HARDWARE_VERSION_BOLLYWOOD
0x21 -> 0x20100001 -> BSP_HARDWARE_VERSION_BOLLYWOOD_PROD_FOR_WII

Field Description
VERHI Version
VERLO Revision


LT_CHIPREVID (0x0d8005a0)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R
Field MAGIC
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R R
Field VERHI VERLO

This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.
Hardware revision -> IOSU equivalent flag -> BSP hardware version
0x10 -> 0x21100010 -> BSP_HARDWARE_VERSION_LATTE_A11_EV
0x10 -> 0x21100020 -> BSP_HARDWARE_VERSION_LATTE_A11_CAT
0x18 -> 0x21200010 -> BSP_HARDWARE_VERSION_LATTE_A12_EV
0x18 -> 0x21200020 -> BSP_HARDWARE_VERSION_LATTE_A12_CAT
0x21 -> 0x22100010 -> BSP_HARDWARE_VERSION_LATTE_A2X_EV
0x21 -> 0x22100020 -> BSP_HARDWARE_VERSION_LATTE_A2X_CAT
0x30 -> 0x23100010 -> BSP_HARDWARE_VERSION_LATTE_A3X_EV
0x30 -> 0x23100020 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAT
0x30 -> 0x23100028 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAFE
0x40 -> 0x24100010 -> BSP_HARDWARE_VERSION_LATTE_A4X_EV
0x40 -> 0x24100020 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAT
0x40 -> 0x24100028 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAFE
0x50 -> 0x25100010 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV
0x50 -> 0x25100011 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV_Y
0x50 -> 0x25100020 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAT
0x50 -> 0x25100028 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAFE
0x60 -> 0x26100010 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV
0x60 -> 0x26100011 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV_Y
0x60 -> 0x26100020 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAT
0x60 -> 0x26100028 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAFE

Field Description
MAGIC Hardcoded to 0xCAFE
VERHI Version
VERLO Revision


HW_IOPWRCTRL (0x0d8001dc)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ? ? R/W R/W R/W R/W R/W ?
Field GPIO GPIO FLA SDIO SI
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ? R/W ? R/W R/W ? ? ?
Field AI VI DI


HW_IOSTRCTRL0 (0x0d8001e0)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ? ? ? R/W R/W ?
Field VI DI
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ? ? ? R/W ? R/W
Field SI AI
Field Description
VI Video Interface IO power control. IOSU sets to 0x3 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.
DI Drive Interface IO power control. IOSU sets to 0x1 on Hollywood hardware, or 0x2 on Bollywood or Latte hardware.
SI Serial Interface IO power control. IOSU sets to 0x1 on Hollywood and Bollywood chipsets, 0x2 on Latte chips.
AI Audio Interface IO power control. IOSU sets to 0x2 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.


HW_SPARE1 (0x0d80018c)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ?
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ? R/W R/W ?
Field DSKPLLSRC BOOT0

This register at least controls the boot0 memory mapping and DSK PLL source.

Field Description
BOOT0 Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
DSKPLLSRC According to STM, setting this to 00 "puts DSKPLL back to external reference"


LT_DEBUG (0x0d8005a4)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field DEBUG
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register at least holds a flag related to DEBUG mode.

Field Description
DEBUG Ask for user input during the IOSU's boot sequence


LT_OTPPROT (0x0d800510)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field BOOT1
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register is a bitmask for locking out chunks of the OTP. Each bit clears out 0x20 bytes of the OTP starting from the bottom (bank 7 is 0xF0000000) to the top (bank 0 is 0x0000000F).

Field Description
BOOT1 Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7