Hardware/Memory controller

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Revision as of 23:01, 4 February 2016 by Hykem (talk | contribs) (Adding memory controller registers)
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Memory controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d8b0000
Length???
Access size32 bits
Byte orderBig Endian
IRQs
Espresso???
Latte???
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Register List

Memory Controller
Address Bits Name Description
0x0d8b080c 16 MEM_AMN_RDBIMASK Unknown
0x0d8b0854 16 MEM_UNK1 Unknown
0x0d8b4226 16 MEM_SELF_REFRESH_MODE Unknown
0x0d8b4228 16 MEM_FLUSHREQ AHB flush request
0x0d8b422a 16 MEM_FLUSHACK AHB flush ack
0x0d8b42c4 16 MEM_WRITE_SEQ_VAL Unknown
0x0d8b42c6 16 MEM_WRITE_SEQ_ADDR Unknown
0x0d8b42cc 16 MEM_EDRAM_REFRESH_CTRL Unknown
0x0d8b42ce 16 MEM_EDRAM_REFRESH_VAL Unknown
0x0d8b42d4 16 MEM_MAP_COMPAT_MODE Unknown
0x0d8b4300 16 MEM_WRITE_SEQ0_VAL Unknown
0x0d8b4302 16 MEM_WRITE_SEQ0_ADDR Unknown

Register Details