Difference between revisions of "Hardware/SATA controller"

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m (Note non-standard registers (work needed to get detail))
m (Hallowizer2 moved page Hardware/SATA Controller to Hardware/SATA controller: sentencecase)
 
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| arm = Full
 
| arm = Full
 
| base = 0x0d160000
 
| base = 0x0d160000
| len = 0x10000
+
| len = 0x808
 
| bits = 32
 
| bits = 32
| ppcirq = ???
+
| latteirq = 6 (LT), 28 (ALL)
| latteirq = ???
 
 
}}
 
}}
  
The Wii U has a mostly standard AHCI 1.2 SATA controller onboard. It identifies as having two ports (0 and 1) running at 3Gbps. In retail systems, the disc drive is connected to port 0; while port 1 is disconnected. Unused code in IOS-BSP indicates that port 7 may be present on non-retail units.
+
The Wii U has a mostly standard AHCI 1.2 SATA controller onboard. It identifies as having two ports (0 and 1) capable of 3Gbps. In retail systems, the disc drive is connected to port 0; while port 1 is disconnected.
  
In terms of hardware registers; the controller lines up with the specification starting at address 0x0D160400; that is; the first Generic Host Control register (Host Capabilities) resides at 0x0D160400. On a retail console, this register reads out 0x7720FF81.
+
In terms of hardware registers; the controller lines up with the specification starting at address 0x0D160400; that is; the first Generic Host Control register (Host Capabilities) resides at 0x0D160400. On a retail console, this register reads out 0x7720FF81. The controller is not entirely standard, however - only 6 ports worth of MMIO space has been allocated, after which a custom set of interrupt control registers exist.
  
== Registers ==
+
== Interrupts ==
* The generic host control registers start at 0x0D160400.
+
The Wii U's SATA controller uses custom interrupt routing "in front" of the standard AHCI mechanism. The IOSU masks and acknowledges IRQs in both the custom registers and the standard ones - it appears an IRQ must be enabled in both the AHCI registers and the custom IRQ controller for it to be delivered to the {{hw|Latte IRQ Controller}} (LT #6).
* The port registers start at 0x0D160500.
 
* There appears to be a non-standard set of interrupt control registers after the main AHCI register area.
 
 
 
== ATAPI commands ==
 
Besides commands defined in the ATAPI specification, the Wii U also seems to have some custom commands.
 
 
 
=== 0xDA - ATAPI_DI_READ_DISC_INFORMATION_CMD ===
 
 
 
=== 0xE0 - ATAPI_DI_REQUEST_ERROR_ID_CMD ===
 
  
=== 0xED - ATAPI_DI_READ_CBC_CMD ===
+
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 
+
|- style="background-color: #ddd;"
=== 0xF0 - ATAPI_CF_REQUEST_DRIVE_ID_CMD ===
+
! IRQ
 
 
=== 0xF1 - ATAPI_CF_AUTHENTICATE_CMD ===
 
 
 
=== 0xF2 - ATAPI_CF_START_STOP_UNIT_CMD ===
 
 
 
=== 0xF3 - ATAPI_CF_READ_CMD ===
 
 
 
=== 0xF4 - ATAPI_CF_TEST_UNIT_READY_CMD ===
 
 
 
=== 0xF5 - ATAPI_CF_INQUIRY_CMD ===
 
{| class="wikitable"
 
|-
 
! Offset
 
! Size
 
 
! Description
 
! Description
 
|-
 
|-
| 0x00
+
| 0 || Unknown (disc inserted?)
| 0x02
 
| Unknown
 
 
|-
 
|-
| 0x02
+
| 1 || Unknown
| 0x01
 
| Vendor
 
 
|-
 
|-
| 0x03
+
| 3 || AHCI Port 0 IRQ
| 0x01
 
| Device
 
 
|-
 
|-
| 0x04
+
| 5 || AHCI Port 1 IRQ
| 0x1C
 
| Unknown
 
 
|-
 
|-
| 0x20
 
| -
 
| End
 
 
|}
 
|}
  
=== 0xFB - ATAPI_CF_FREC_READ_CMD ===
+
The SATA controller also owns Latte IRQ ALL #28. It's unknown what this is used for, but an IOSU debug string suggests it can deliver spurious "DBGINT"s in some situations.
 +
 
 +
== Registers ==
 +
* The generic host control registers start at 0x0D160400.
 +
* The port registers start at 0x0D160500.
 +
* The port registers *finish* at 0x0D160800, while the AHCI spec requires them to end at 0x0D161100.
 +
 
 +
{{regsimple|SATA_HCCFG_INT_REG|addr=0x0d160800|bits=32|access=R/W}}
 +
This register contains the IRQ flag bits. These are set by the hardware. To clear a flag, write 1 to it.
 +
 
 +
{{regsimple|SATA_HCCFG_INTMSK_REG|addr=0x0d160804|bits=32|access=R/W}}
 +
This register contains the IRQ mask bits. If a bit is set, then the corresponding flag bit will cause Latte IRQ LT #7 to be asserted.
  
 
== See Also ==
 
== See Also ==
 
[https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1_2.pdf AHCI 1.2 spec]
 
[https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1_2.pdf AHCI 1.2 spec]

Latest revision as of 05:34, 10 August 2021

SATA controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d160000
Length0x808
Access size32 bits
Byte orderBig Endian
Latte6 (LT), 28 (ALL)
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The Wii U has a mostly standard AHCI 1.2 SATA controller onboard. It identifies as having two ports (0 and 1) capable of 3Gbps. In retail systems, the disc drive is connected to port 0; while port 1 is disconnected.

In terms of hardware registers; the controller lines up with the specification starting at address 0x0D160400; that is; the first Generic Host Control register (Host Capabilities) resides at 0x0D160400. On a retail console, this register reads out 0x7720FF81. The controller is not entirely standard, however - only 6 ports worth of MMIO space has been allocated, after which a custom set of interrupt control registers exist.

Interrupts

The Wii U's SATA controller uses custom interrupt routing "in front" of the standard AHCI mechanism. The IOSU masks and acknowledges IRQs in both the custom registers and the standard ones - it appears an IRQ must be enabled in both the AHCI registers and the custom IRQ controller for it to be delivered to the Latte IRQ Controller (LT #6).

IRQ Description
0 Unknown (disc inserted?)
1 Unknown
3 AHCI Port 0 IRQ
5 AHCI Port 1 IRQ

The SATA controller also owns Latte IRQ ALL #28. It's unknown what this is used for, but an IOSU debug string suggests it can deliver spurious "DBGINT"s in some situations.

Registers

  • The generic host control registers start at 0x0D160400.
  • The port registers start at 0x0D160500.
  • The port registers *finish* at 0x0D160800, while the AHCI spec requires them to end at 0x0D161100.

SATA_HCCFG_INT_REG (0x0d160800)
  310
Access R/W

This register contains the IRQ flag bits. These are set by the hardware. To clear a flag, write 1 to it.

SATA_HCCFG_INTMSK_REG (0x0d160804)
  310
Access R/W

This register contains the IRQ mask bits. If a bit is set, then the corresponding flag bit will cause Latte IRQ LT #7 to be asserted.

See Also

AHCI 1.2 spec