Hardware/SATA controller

From WiiUBrew
< Hardware
Revision as of 12:13, 30 July 2021 by QuarkTheAwesome (talk | contribs) (Add IRQ controller info)
Jump to navigation Jump to search
SATA controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d160000
Length0x808
Access size32 bits
Byte orderBig Endian
Latte6 (LT), 28 (ALL)
This box: view  talk  edit

The Wii U has a mostly standard AHCI 1.2 SATA controller onboard. It identifies as having two ports (0 and 1) capable of 3Gbps. In retail systems, the disc drive is connected to port 0; while port 1 is disconnected.

In terms of hardware registers; the controller lines up with the specification starting at address 0x0D160400; that is; the first Generic Host Control register (Host Capabilities) resides at 0x0D160400. On a retail console, this register reads out 0x7720FF81. The controller is not entirely standard, however - only 6 ports worth of MMIO space has been allocated, after which a custom set of interrupt control registers exist.

Interrupts

The Wii U's SATA controller uses custom interrupt routing "in front" of the standard AHCI mechanism. The IOSU masks and acknowledges IRQs in both the custom registers and the standard ones - it appears an IRQ must be enabled in both the AHCI registers and the custom IRQ controller for it to be delivered to the Latte IRQ Controller (LT #6).

IRQ Description
0 Unknown (disc inserted?)
1 Unknown
3 AHCI Port 0 IRQ
5 AHCI Port 1 IRQ

The SATA controller also owns Latte IRQ ALL #28. It's unknown what this is used for, but an IOSU debug string suggests it can deliver spurious "DBGINT"s in some situations.

Registers

  • The generic host control registers start at 0x0D160400.
  • The port registers start at 0x0D160500.
  • The port registers *finish* at 0x0D160800, while the AHCI spec requires them to end at 0x0D161100.

SATA_HCCFG_INT_REG (0x0d160800)
  310
Access R/W

This register contains the IRQ flag bits. These are set by the hardware. To clear a flag, write 1 to it.

SATA_HCCFG_INTMSK_REG (0x0d160804)
  310
Access R/W

This register contains the IRQ mask bits. If a bit is set, then the corresponding flag bit will cause Latte IRQ LT #7 to be asserted.

ATAPI commands

Besides commands defined in the ATAPI specification, the Wii U also seems to have some custom commands.

0xDA - ATAPI_DI_READ_DISC_INFORMATION_CMD

0xE0 - ATAPI_DI_REQUEST_ERROR_ID_CMD

0xED - ATAPI_DI_READ_CBC_CMD

0xF0 - ATAPI_CF_REQUEST_DRIVE_ID_CMD

0xF1 - ATAPI_CF_AUTHENTICATE_CMD

0xF2 - ATAPI_CF_START_STOP_UNIT_CMD

0xF3 - ATAPI_CF_READ_CMD

0xF4 - ATAPI_CF_TEST_UNIT_READY_CMD

0xF5 - ATAPI_CF_INQUIRY_CMD

Offset Size Description
0x00 0x02 Unknown
0x02 0x01 Vendor
0x03 0x01 Device
0x04 0x1C Unknown
0x20 - End

0xFB - ATAPI_CF_FREC_READ_CMD

See Also

AHCI 1.2 spec