Changes

Jump to navigation Jump to search
3,406 bytes added ,  19:47, 19 November 2019
no edit summary
| arm = Full
| ppc = Partial
| base = 0x0d8000c0, 0x0d800520| len = 0x400x80
| bits = 32
| ppcirq = None
}}
The Latte chipset includes at least 29 two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LT). Two Four sets of registers are provided(two for each group), and the Espresso only has access to one settwo sets. This set accesses These sets access a configurable subset of the IO pins, which the Starbuck can select.
== Pin connections ==
|-
! Bit
! Group
! Direction
! Connection
! Description
|-
| 0 || ALL || IN || SYS_INT RTCSysInt || Power button input (RTCSysInt, FanSpeed and/or ToucanSelect).
|-
| 1 0 || LT || OUT || DWIFI_MODE FanSpeed || Unknown (DWiFiMode and/or SMCI2CClock)Fan speed.
|-
| 2 0 || OUT ALL || FAN_PWR I/O || ToucanSelect || Fan power, active high "Toucan" select (FanPower and/or SMCI2CDatadevkit only).
|-
| 3 1 || ALL || OUT || DC_DC DWiFiMode || DC/DC converter power (DCDCPwrCnt, DCDCPwrCnt2 and/or CCRIO3), active highDWiFi mode.
|-
| 4 1 || OUT LT || AV_INT IN || A/V Encoder interrupt SMCI2CClock || SMC (AVInterruptsurface mounted components)?I²C Clock.
|-
| 5 2 || ALL || OUT || ESP10_FIX FanPower || Unknown (ESP10WorkAround and/or CCRIO12)Fan power, active high.
|-
| 6 2 || OUT LT || AV_RST IN || A/V Encoder reset SMCI2CData || SMC (AVResetsurface mounted components)?I²C Data.
|-
| 7 3 || UNK ALL || UNKNOWN OUT || UnknownDCDCPwrCnt || DC/DC converter power, active high.
|-
| 8 3 || LT || OUT || SDC_PWR DCDCPwrCnt2 || Unknown (SDC0S0Power andDC/or PADPD)DC converter power, active high.
|-
| 9 3 || UNK ALL || UNKNOWN OUT || CCRIO3 || Unknown.(duplicate?)
|-
| 10 4 || OUT ALL || EEPROM_CS UNK || SEEPROM Chip SelectUNKNOWN || Unknown.
|-
| 11 4 || OUT LT || EEPROM_SK IN || SEEPROM ClockAVInterrupt || A/V encoder interrupt (from Espresso).
|-
| 12 5 || ALL || OUT || EEPROM_DO ESP10WorkAround || Data to SEEPROMUnknown.
|-
| 13 5 || IN LT || EEPROM_DI OUT || Data from SEEPROMCCRIO12 || Unknown.
|-
| 14 6 || OUT ALL || AV0_I2C_CLOCK UNK || A/V Encoder (#0) I²C ClockUNKNOWN || Unknown.
|-
| 15 6 || I/O LT || OUT || AV0_I2C_DATAAVReset || A/V Encoder encoder reset (#0from Espresso) I²C Data.
|-
| 16 7 || OUT ALL || NDEV_LED UNK || DevKit LED?UNKNOWN || Unknown.
|-
| 17 8 || ALL || OUT || DEBUG1 PADPD || Debug?Gamepad power state.
|-
| 18 9 || OUT ALL || DEBUG2 UNK || Debug?UNKNOWN || Unknown.
|-
| 19 10 || ALL || OUT || DEBUG3 EEPROM_CS || Debug?SEEPROM Chip Select.
|-
| 20 11 || ALL || OUT || DEBUG4 EEPROM_SK || Debug?SEEPROM Clock.
|-
| 21 12 || ALL || OUT || DEBUG5 EEPROM_DO || Debug?Data to SEEPROM.
|-
| 22 13 || OUT ALL || DEBUG6 IN || Debug?EEPROM_DI || Data from SEEPROM.
|-
| 23 14 || ALL || OUT || DEBUG7 AV0I2CClock || Debug?A/V Encoder (#0) I²C Clock.
|-
| 24 15 || ALL || OUT || AV1_I2C_CLOCK AV0I2CData || A/V Encoder (#10) I²C ClockData.
|-
| 25 16 || ALL || I/O || AV1_I2C_DATA NDEV_LED || A/V Encoder Development unit's LED (#1devkit only) I²C Data.
|-
| 26 16 || ALL || OUT || MUTE_LAMP DEBUG0 || UnknownDebug Testpoint.
|-
| 27 17 || ALL || OUT || BT_MODE DEBUG1 || BlueTooth modeDebug Testpoint.
|-
| 28 18 || ALL || OUT || CCRH_RST DEBUG2 || CCRH resetDebug Testpoint.
|-
| 19 || ALL || OUT || DEBUG3 || Debug Testpoint.|-| 20 || ALL || OUT || DEBUG4 || Debug Testpoint.|-| 21 || ALL || OUT || DEBUG5 || Debug Testpoint.|-| 22 || ALL || OUT || DEBUG6 || Debug Testpoint.|-| 23 || ALL || OUT || DEBUG7 || Debug Testpoint.|-| 24 || ALL || OUT || AV1I2CClock || A/V Encoder (#1) I²C Clock.|-| 25 || ALL || OUT || AV1I2CData || A/V Encoder (#1) I²C Data.|-| 26 || ALL || OUT || MuteLamp || Unknown.|-| 27 || ALL || OUT || BlueToothMode || BlueTooth mode.|-| 28 || ALL || OUT || CCRHReset || CCR (constant current regulator?) hard reset.|-| 29 || ALL || OUT || WIFI_MODE WiFiMode || WiFi mode.|-| 30 || ALL || OUT || SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card.
|}
== Register list ==
{{reglist|Wood and Latte GPIOs(ALL)}}{{rla|0x0d8000c0|32|LT_GPIOE_OUTHW_GPIOB_OUT|GPIO Outputs (Espresso access)}}{{rla|0x0d8000c4|32|LT_GPIOE_DIRHW_GPIOB_DIR|GPIO Direction (Espresso access)}}{{rla|0x0d8000c8|32|LT_GPIOE_INHW_GPIOB_IN|GPIO Inputs (Espresso access)}}{{rla|0x0d8000cc|32|LT_GPIOE_INTLVLHW_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}{{rla|0x0d8000d0|32|LT_GPIOE_INTFLAGHW_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}{{rla|0x0d8000d4|32|LT_GPIOE_INTMASKHW_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}{{rla|0x0d8000d8|32|LT_GPIOE_INMIRHW_GPIOB_STRAPS|GPIO Input Mirror Straps (Espresso access)}}{{rla|0x0d8000dc|32|LT_GPIO_ENABLEHW_GPIO_ENABLE|GPIO Enable (Starbuck only)}}{{rla|0x0d8000e0|32|LT_GPIO_OUTHW_GPIO_OUT|GPIO Outputs (Starbuck only)}}{{rla|0x0d8000e4|32|LT_GPIO_DIRHW_GPIO_DIR|GPIO Direction (Starbuck only)}}{{rla|0x0d8000e8|32|LT_GPIO_INHW_GPIO_IN|GPIO Inputs (Starbuck only)}}{{rla|0x0d8000ec|32|LT_GPIO_INTLVLHW_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}{{rla|0x0d8000f0|32|LT_GPIO_INTFLAGHW_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}{{rla|0x0d8000f4|32|LT_GPIO_INTMASKHW_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}{{rla|0x0d8000f8|32|LT_GPIO_INMIRHW_GPIO_STRAPS|GPIO Input Mirror Straps (Starbuck only)}}{{rla|0x0d8000fc|32|HW_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}|}  {{reglist|Latte GPIOs (LT)}}{{rla|0x0d800520|32|LT_GPIOB_OUT|GPIO Outputs (Espresso access)}}{{rla|0x0d800524|32|LT_GPIOB_DIR|GPIO Direction (Espresso access)}}{{rla|0x0d800528|32|LT_GPIOB_IN|GPIO Inputs (Espresso access)}}{{rla|0x0d80052c|32|LT_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}{{rla|0x0d800530|32|LT_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}{{rla|0x0d800534|32|LT_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}{{rla|0x0d800538|32|LT_GPIOB_STRAPS|GPIO Straps (Espresso access)}}{{rla|0x0d80053c|32|LT_GPIO_ENABLE|GPIO Enable (Starbuck only)}}{{rla|0x0d800540|32|LT_GPIO_OUT|GPIO Outputs (Starbuck only)}}{{rla|0x0d800544|32|LT_GPIO_DIR|GPIO Direction (Starbuck only)}}{{rla|0x0d800548|32|LT_GPIO_IN|GPIO Inputs (Starbuck only)}}{{rla|0x0d80054c|32|LT_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}{{rla|0x0d800550|32|LT_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}{{rla|0x0d800554|32|LT_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}{{rla|0x0d800558|32|LT_GPIO_STRAPS|GPIO Straps (Starbuck only)}}{{rla|0x0d80055c|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
|}
== Register descriptions ==
{{regsimple2|LT_GPIO_ENABLEHW_GPIO_ENABLE|addr=0x0d8000dc|bits=32|split=24|access=R/W}}
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
----
{{regsimple2|LT_GPIO_OUTHW_GPIO_OUT|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
----
{{regsimple2|LT_GPIO_DIRHW_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
----
{{regsimple2|LT_GPIO_INHW_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}
This register can be read to obtain the current input value of the GPIO pins.
----
{{regsimple2|LT_GPIO_INTLVLHW_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
----
{{regsimple2|LT_GPIO_INTFLAGHW_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the LT_GPIO_INTLVL HW_GPIO_INTLVL register, then the corresponding bit in LT_GPIO_INTFLAG HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in LT_GPIO_INTLVL HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
----
{{regsimple2|LT_GPIO_INTMASKHW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|Latte GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#LT_GPIO_INTFLAG|LT_GPIO_INTFLAG]]HW_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is LT_GPIO_INTMASK HW_GPIO_INTMASK & LT_GPIO_INTFLAG HW_GPIO_INTFLAG & ~LT_GPIO_OWNERHW_GPIO_OWNER.
----
{{regsimple2|LT_GPIO_INMIRHW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. {{check}}
----
{{regsimple2|LT_GPIO_OWNERHW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}This register configures which pins can be controlled by the LT_GPIOE HW_GPIOB_* registers. A one bit configures the pin for control via the LT_GPIOE HW_GPIOB_* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO HW_GPIO_* registers, which are Starbuck-only. The LT_GPIO HW_GPIO_* registers always have read access to all pins, but any writes (changes) must go through the LT_GPIOB HW_GPIOB_* registers if the corresponding bit is set in the LT_GPIO_OWNER HW_GPIO_OWNER register.
----
{{regsimple2|LT_GPIOE_OUTHW_GPIOB_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOE_DIRHW_GPIOB_DIR|addr=0x0d8000c4|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOE_INHW_GPIOB_IN|addr=0x0d8000c8|bits=32|split=24|access=R}}{{regsimple2|LT_GPIOE_INTLVLHW_GPIOB_INTLVL|addr=0x0d8000cc|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOE_INTFLAGHW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}{{regsimple2|LT_GPIOE_INTMASKHW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOE_INMIRHW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}These registers operate identically to their LT_GPIO HW_GPIO_* counterparts above, but they only control the pins which have their respective [[#LT_GPIO_OWNER|LT_GPIO_OWNER]] HW_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|Latte GPIOE GPIOB interrupt]] (#10). The generation logic would be LT_GPIOE_INTFLAG HW_GPIOB_INTFLAG & LT_GPIOE_INTMASKHW_GPIOB_INTMASK, with an implicit AND with LT_GPIO_OWNER HW_GPIO_OWNER since the GPIOE HW_GPIOB_* registers are already masked with the LT_GPIO_OWNER HW_GPIO_OWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO HW_GPIO_* registers, and that bit is then set in the LT_GPIO_OWNER HW_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE HW_GPIOB_* registers. There is only one set of data registers, and the LT_GPIO_OWNER HW_GPIO_OWNER register just controls the access that the LT_GPIOE HW_GPIOB_* registers have to that data.----{{regsimple2|LT_GPIOB_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOB_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOB_IN|addr=0x0d800528|bits=32|split=24|access=R}}{{regsimple2|LT_GPIOB_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOB_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}{{regsimple2|LT_GPIOB_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIOB_STRAPS|addr=0x0d800538|bits=32|split=24|access=R}}{{regsimple2|LT_GPIO_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIO_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIO_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIO_IN|addr=0x0d800548|bits=32|split=24|access=R}}{{regsimple2|LT_GPIO_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIO_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}{{regsimple2|LT_GPIO_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}{{regsimple2|LT_GPIO_STRAPS|addr=0x0d800558|bits=32|split=24|access=R}}{{regsimple2|LT_GPIO_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}These registers work identically to those used for the first GPIO group.
76

edits

Navigation menu