Changes

90 bytes removed ,  20:25, 19 November 2019
no edit summary
Note that, since the interrupts can actually route to either or both the Starbuck and Espresso, and since the Starbuck can also access the Espresso's registers, there are ways of abusing these flags for odd purposes.
Register LT_IPC_ARMCTRL Registers HW_IPC_ARMCTRL and LT_IPC_ARMCTRLx can only be accessed by the Starbuck. The other three registers others can be accessed by both CPUs.
== Register List ==
The Latte IPC engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores. Each core's region of the SMP block has registers equivalent to the old global block.
===Compat Wood block==={{reglist|Global compat Wood block}}{{rla|0x0d800000|32|LT_IPC_PPCMSG_COMPATHW_IPC_PPCMSG|Espresso data register for vWii}}{{rla|0x0d800004|32|LT_IPC_PPCCTRL_COMPATHW_IPC_PPCCTRL|Espresso flags and control for vWii}}{{rla|0x0d800008|32|LT_IPC_ARMMSG_COMPATHW_IPC_ARMMSG|Starbuck data register for vWii}}{{rla|0x0d80000c|32|LT_IPC_ARMCTRL_COMPATHW_IPC_ARMCTRL|Starbuck flags and control for vWii}}
|}
===SMP Latte block==={{reglist|SMP Latte block - PPC core 0}}{{rla|0x0d800400|32|LT_IPC_PPC0_PPCMSGLT_IPC_PPCMSG0|Espresso data register for PPC core 0}}{{rla|0x0d800404|32|LT_IPC_PPC0_PPCCTRLLT_IPC_PPCCTRL0|Espresso flags and control for PPC core 0}}{{rla|0x0d800408|32|LT_IPC_PPC0_ARMMSGLT_IPC_ARMMSG0|Starbuck data register for PPC core 0}}{{rla|0x0d80040c|32|LT_IPC_PPC0_ARMCTRLLT_IPC_ARMCTRL0|Starbuck flags and control for PPC core 0}}
|}
{{reglist|SMP Latte block - PPC core 1}}{{rla|0x0d800410|32|LT_IPC_PPC1_PPCMSGLT_IPC_PPCMSG1|Espresso data register for PPC core 1}}{{rla|0x0d800414|32|LT_IPC_PPC1_PPCCTRLLT_IPC_PPCCTRL1|Espresso flags and control for PPC core 1}}{{rla|0x0d800418|32|LT_IPC_PPC1_ARMMSGLT_IPC_ARMMSG1|Starbuck data register for PPC core 1}}{{rla|0x0d80041c|32|LT_IPC_PPC1_ARMCTRLLT_IPC_ARMCTRL1|Starbuck flags and control for PPC core 1}}
|}
{{reglist|SMP Latte block - PPC core 2}}{{rla|0x0d800420|32|LT_IPC_PPC2_PPCMSGLT_IPC_PPCMSG2|Espresso data register for PPC core 2}}{{rla|0x0d800424|32|LT_IPC_PPC2_PPCCTRLLT_IPC_PPCCTRL2|Espresso flags and control for PPC core 2}}{{rla|0x0d800428|32|LT_IPC_PPC2_ARMMSGLT_IPC_ARMMSG2|Starbuck data register for PPC core 2}}{{rla|0x0d80042c|32|LT_IPC_PPC2_ARMCTRLLT_IPC_ARMCTRL2|Starbuck flags and control for PPC core 2}}
|}
== Register Details ==
{{regsimple | LT_IPC_PPCx_PPCMSG LT_IPC_PPCMSGx | addr = 0x0d800400/0x0d800410/0x0d800420 | bits = 32 | access = R/W }}
This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Espresso and read by the Starbuck, though this is not a requirement. In IOSU, this register contains a pointer to a [[IOSU#IPC|0x48-byte structure in memory]].
----
{{reg32 | LT_IPC_PPCx_PPCCTRL LT_IPC_PPCCTRLx | addr = 0x0d800404/0x0d800414/0x0d800424 | hifields = 1 | lofields = 7 |
|16|
|U|
}}
This register exposes the Espresso side of the IPC control. Flags X1 and X2 may be freely set/cleared. Flags Y1 and Y2 can be read and cleared (by writing one), and can optionally generate IRQ #30.
 ===IOS usage===
{{regdesc
|X1|Execute command: a new pointer is available in ''in LT_IPC_PPCx_PPCCTRLLT_IPC_PPCCTRLx''
|Y2|Command acknowledge
|Y1|Command executed and reply available in ''LT_IPC_PPCx_ARMMSGLT_IPC_ARMMSGx''
|X2|Relaunch
}}
----
{{regsimple | LT_IPC_PPCx_ARMMSG LT_IPC_ARMMSGx | addr = 0x0d800408/0x0d800418/0x0d800428 | bits = 32 | access = R/W }}
This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starbuck and read by the Espresso, though this is not a requirement.
----
{{reg32 | LT_IPC_PPCx_ARMCTRL LT_IPC_ARMCTRLx | addr = 0x0d80040c/0x0d80041c/0x0d80042c | hifields = 1 | lofields = 7 |
|16|
|U|
76

edits