|Access size||32 bits|
|Byte order||Big Endian|
|Latte||6 (LT), 28 (ALL)|
The Wii U has a mostly standard AHCI 1.2 SATA controller onboard. It identifies as having two ports (0 and 1) capable of 3Gbps. In retail systems, the disc drive is connected to port 0; while port 1 is disconnected.
In terms of hardware registers; the controller lines up with the specification starting at address 0x0D160400; that is; the first Generic Host Control register (Host Capabilities) resides at 0x0D160400. On a retail console, this register reads out 0x7720FF81. The controller is not entirely standard, however - only 6 ports worth of MMIO space has been allocated, after which a custom set of interrupt control registers exist.
The Wii U's SATA controller uses custom interrupt routing "in front" of the standard AHCI mechanism. The IOSU masks and acknowledges IRQs in both the custom registers and the standard ones - it appears an IRQ must be enabled in both the AHCI registers and the custom IRQ controller for it to be delivered to the Latte IRQ Controller (LT #6).
|0||Unknown (disc inserted?)|
|3||AHCI Port 0 IRQ|
|5||AHCI Port 1 IRQ|
The SATA controller also owns Latte IRQ ALL #28. It's unknown what this is used for, but an IOSU debug string suggests it can deliver spurious "DBGINT"s in some situations.
- The generic host control registers start at 0x0D160400.
- The port registers start at 0x0D160500.
- The port registers *finish* at 0x0D160800, while the AHCI spec requires them to end at 0x0D161100.
This register contains the IRQ flag bits. These are set by the hardware. To clear a flag, write 1 to it.
This register contains the IRQ mask bits. If a bit is set, then the corresponding flag bit will cause Latte IRQ LT #7 to be asserted.