Hardware/AHMN controller

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AHMN controller
Access size32 bits
Byte orderBig Endian
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The AHM (AHB_MEM) was a custom bridge responsible for connecting the AHB bus to the Memory Controller in the old Hollywood's chipset.
The Latte hardware contains an enhanced version of this bridge dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).

Registers with the AHM_* prefix pertain to the old, base hardware block. Registers with the AHMN_* prefix pertain to the new, enhanced hardware block.

Register List

AHMN Controller
Address Bits Name Description
0x0d8b0000 32 AHM_PROTDDR AHM configuration for DDR protection
0x0d8b0004 32 AHM_PROTSPL AHM configuration for SPL protection
0x0d8b0008 32 AHM_RDBI AHM read buffer invalidate mask
0x0d8b0020 32 AHM_INTMSK AHM interrupt mask
0x0d8b0030 32 AHM_INTSTS AHM interrupt status
0x0d8b0800 32 AHMN_PROTMEM0 AHMN configuration for MEM0 protection
0x0d8b0804 32 AHMN_PROTMEM1 AHMN configuration for MEM1 protection
0x0d8b0808 32 AHMN_PROTMEM2 AHMN configuration for MEM2 protection
0x0d8b080c 32 AHMN_RDBI AHMN read buffer invalidate mask
0x0d8b0820 32 AHMN_INTMSK AHMN interrupt mask
0x0d8b0824 32 AHMN_INTSTS AHMN interrupt status
0x0d8b0840 32 AHMN_UNK Unknown
0x0d8b0844 32 AHMN_UNK Unknown
0x0d8b0850 32 AHMN_TRFSTS AHMN transfer status
0x0d8b0854 32 AHMN_WORKAROUND Unknown
0x0d8b0900...0x0d8b0980 32 AHMN_MEM0 Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)
0x0d8b0a00...0x0d8b0c00 32 AHMN_MEM1 Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)
0x0d8b0c00...0x0d8b1000 32 AHMN_MEM2 Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)

Register Details