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| arm = Full
| base = 0x0d800030, 0x0d800440
| len = 0x100x14, 0x48
| bits = 32
}}
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LT). ==IRQ Sources==
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
! IRQ
! Group
! Description
|-
| 0 || ALL || Timer (Starbuck)|-| 1 || ALL || {{hw|NAND Interface}}|-| 2 || ALL || {{hw|AES Engine}}|-| 3 || ALL || {{hw|SHA-1 Engine}}|-| 4 || ALL || {{hw|Starbuck TimerUSB Host Controller}} (EHCI-0)|-| 5 || ALL || {{hw|USB Host Controller}}(OHCI-0:0)
|-
| 1 6 || ALL || {{hw|NAND InterfaceUSB Host Controller}}(OHCI-0:1)
|-
| 2 7 || ALL || {{hw|AES EngineSD Host Controller}}
|-
| 3 8 || ALL || {{hw|SHA-1 Engine802.11 Wireless}}
|-
| 4 9 || {{hwALL |USB Host Controller}} (EHCI)| Undefined
|-
| 5 10 || ALL || {{hw|USB Host ControllerLatte GPIOs}} (OHCI0Espresso)
|-
| 6 11 || ALL || {{hw|USB Host ControllerLatte GPIOs}} (OHCI1Starbuck)
|-
| 7 12 || {{hwALL |SD Host Controller}}| SYSPROT
|-
| 8 13 || {{hwALL |802.11 Wireless}}| Undefined
|-
| 9 14 || UnknownALL || Undefined
|-
| 10 15 || {{hwALL |Latte GPIOs}} (Espresso)| Undefined
|-
| 11 16 || ALL || {{hw|Latte GPIOsUSB Host Controller}} (StarbuckEHCI-1)
|-
| 12 17 || UnknownALL || Power button
|-
| 13 18 || UndefinedALL || Drive Interface
|-
| 14 19 || ALL || Undefined
|-
| 15 20 || UndefinedALL || EXI RTC
|-
| 16 21 || ALL || Undefined
|-
| 17 22 || Power button (reset)ALL || Undefined
|-
| 18 23 || {{hwALL |Drive Interface}} (DI)| Undefined
|-
| 19 24 || ALL || Undefined
|-
| 20 25 || UnknownALL || Undefined
|-
| 21 26 || ALL || Undefined
|-
| 22 27 || ALL || Undefined
|-
| 23 28 || UndefinedALL || SATA
|-
| 24 29 || ALL || Undefined
|-
| 25 30 || UndefinedALL || {{hw|IPC}} (Espresso compat)
|-
| 26 31 || UndefinedALL || {{hw|IPC}} (Starbuck compat)
|-
| 27 0 || UndefinedLT || {{hw|SD Host Controller}}
|-
| 28 1 || {{hwLT |Advanced Host Controller Interface}} (AHCI)| Unknown
|-
| 29 2 || UndefinedLT || Unknown
|-
| 30 3 || LT || {{hw|IPCUSB Host Controller}} (EspressoOHCI-1:0)
|-
| 4 || LT || {{hw|USB Host Controller}} (EHCI-2)|-| 5 || LT || {{hw|USB Host Controller}} (OHCI-2:0)|-| 6 || LT || Unknown|-| 7 || LT || Unknown|-| 8 || LT || {{hw|AES Engine}} (AESS)|-| 9 || LT || {{hw|SHA-1 Engine}} (SHAS-1)|-| 10 || LT || Unknown|-| 11 || LT || Unknown|-| 12 || LT || Unknown|-| 13 || LT || I2C (Espresso)|-| 14 || LT || I2C (Starbuck)|-| 15 || LT || Undefined|-| 16 || LT || Undefined|-| 17 || LT || Undefined|-| 18 || LT || Undefined|-| 19 || LT || Undefined|-| 20 || LT || Undefined|-| 21 || LT || Undefined|-| 22 || LT || Undefined|-| 23 || LT || Undefined|-| 24 || LT || Undefined|-| 25 || LT || Undefined|-| 26 || LT || {{hw|IPC}} (Espresso CPU2)|-| 27 || LT || {{hw|IPC}} (Starbuck CPU2)|-| 28 || LT || {{hw|IPC}} (Espresso CPU1)|-| 29 || LT || {{hw|IPC}} (Starbuck CPU1)|-| 30 || LT || {{hw|IPC}} (Espresso CPU0)|-| 31 || LT || {{hw|IPC}} (StarbuckCPU0)
|-
|}
==Register List==The Latte IRQ controller Each CPU has an independent set of control registers and this set is subdivided into two different register main blocks: a global ARM block mapped at the same address one for Wood and Latte hardware and another exclusive to Latte hardware.The subset used for Latte is further subdivided as on the Wii, and a new SMP block for each that serves the 3 PPC cores and the ARM core to use. ===Global ARM Wood block==={{reglist|Global ARM Wood block}}{{rla|0x0d800030|32|LT_INTSR_PPCHW_PPCIRQFLAG|Triggered IRQs for the PPCcore in vWii}}{{rla|0x0d800034|32|LT_INTMR_PPCHW_PPCIRQMASK|Allowed IRQs for the PPCcore in vWii}}{{rla|0x0d800038|32|LT_INTSR_ARMHW_ARMIRQFLAG|Triggered IRQs for the ARMcore in vWii}}{{rla|0x0d80003c|32|LT_INTMR_ARMHW_ARMIRQMASK|Allowed IRQs for the ARMcore in vWii}}{{rld|0x0d800040|32|HW_ARMFIQMASK|Allowed FIQs for the ARM core in vWii}}|} === Latte block ==={{reglist|Latte block - PPC core 0}}{{rla|0x0d800440|32|LT_PPCIRQFLAGALL0|Triggered IRQs for PPC core 0 (all)}}{{rla|0x0d800444|32|LT_PPCIRQFLAGLT0|Triggered IRQs for PPC core 0 (Latte only)}}{{rla|0x0d800448|32|LT_PPCIRQMASKALL0|Allowed IRQs for PPC core 0 (all)}}{{rla|0x0d80044c|32|LT_PPCIRQMASKLT0|Allowed IRQs for PPC core 0 (Latte only)}}
|}
===SMP block==={{reglist|SMP Latte block - PPC core 01}}{{rla|0x0d8004400x0d800450|32|LT_INTSR_AHBALL_PPC0LT_PPCIRQFLAGALL1|Triggered AHB (all) IRQs for PPC core 01 (all)}}{{rla|0x0d8004440x0d800454|32|LT_INTSR_AHBLT_PPC0LT_PPCIRQFLAGLT1|Triggered AHB (Latte) IRQs for PPC core 01 (Latte only)}}{{rla|0x0d8004480x0d800458|32|LT_INTMR_AHBALL_PPC0LT_PPCIRQMASKALL1|Allowed AHB (all) IRQs for PPC core 01 (all)}}{{rla|0x0d80044c0x0d80045c|32|LT_INTMR_AHBLT_PPC0LT_PPCIRQMASKLT1|Allowed AHB (Latte) IRQs for PPC core 01 (Latte only)}}
|}
{{reglist|SMP Latte block - PPC core 12}}{{rla|0x0d8004500x0d800460|32|LT_INTSR_AHBALL_PPC1LT_PPCIRQFLAGALL2|Triggered AHB (all) IRQs for PPC core 12 (all)}}{{rla|0x0d8004540x0d800464|32|LT_INTSR_AHBLT_PPC1LT_PPCIRQFLAGLT2|Triggered AHB (Latte) IRQs for PPC core 12 (Latte only)}}{{rla|0x0d8004580x0d800468|32|LT_INTMR_AHBALL_PPC1LT_PPCIRQMASKALL2|Allowed AHB (all) IRQs for PPC core 12 (all)}}{{rla|0x0d80045c0x0d80046c|32|LT_INTMR_AHBLT_PPC1LT_PPCIRQMASKLT2|Allowed AHB (Latte) IRQs for PPC core 12 (Latte only)}}
|}
{{reglist|SMP Latte block - PPC ARM core 2}}{{rla|0x0d8004600x0d800470|32|LT_INTSR_AHBALL_PPC2LT_ARMIRQFLAGALL|Triggered AHB IRQs for ARM core (all) IRQs for PPC core 2}}{{rla|0x0d8004640x0d800474|32|LT_INTSR_AHBLT_PPC2LT_ARMIRQFLAGLT|Triggered AHB IRQs for ARM core (Latteonly) }}{{rla|0x0d800478|32|LT_ARMIRQMASKALL|Allowed IRQs for PPC ARM core 2(all)}}{{rla|0x0d8004680x0d80047c|32|LT_INTMR_AHBALL_PPC2LT_ARMIRQMASKLT|Allowed AHB IRQs for ARM core (allLatte only) IRQs }}{{rld|0x0d800480|32|LT_ARMFIQMASKALL|Allowed FIQs for PPC the ARM core 2(all)}}{{rlarld|0x0d80046c0x0d800484|32|LT_INTMR_AHBLT_PPC2LT_ARMFIQMASKLT|Allowed AHB FIQs for the ARM core (Latteonly) IRQs for PPC core 2}}
|}
 
== Register descriptions ==
{{regsimple|LT_PPCIRQFLAGALLx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
{{regsimple|LT_PPCIRQFLAGLTx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
{{regsimple|LT_PPCIRQMASKALLx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
{{regsimple|LT_PPCIRQMASKLTx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
{{regsimple|LT_ARMIRQFLAGALL|addr=0x0d800470|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
{{regsimple|LT_ARMIRQFLAGLT|addr=0x0d800474|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
{{regsimple|LT_ARMIRQMASKALL|addr=0x0d800478|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
----
{{regsimple|LT_ARMIRQMASKLT|addr=0x0d80047c|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
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