Line 42: |
Line 42: |
| {{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}} | | {{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}} |
| {{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}} | | {{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}} |
− | {{rld|0x0d800084|32|HW_USBDBG1|Unknown}} | + | {{rld|0x0d800084|32|HW_USBDBG1}} |
− | {{rld|0x0d800088|32|HW_USBFRCRST|Unknown}} | + | {{rld|0x0d800088|32|HW_USBFRCRST}} |
− | {{rld|0x0d80008c|32|HW_USBIOTEST|Unknown}} | + | {{rld|0x0d80008c|32|HW_USBIOTEST}} |
| {{rld|0x0d800090|32|HW_ELA_REG_ADDR|CoreSight ELA|drs=4}} | | {{rld|0x0d800090|32|HW_ELA_REG_ADDR|CoreSight ELA|drs=4}} |
| {{rld|0x0d800094|32|HW_ELA_REG_DATA}} | | {{rld|0x0d800094|32|HW_ELA_REG_DATA}} |
Line 93: |
Line 93: |
| {{rld|0x0d800198|32|HW_IFPWRCTRL|Interface power control}} | | {{rld|0x0d800198|32|HW_IFPWRCTRL|Interface power control}} |
| {{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=13}} | | {{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=13}} |
− | {{rld|0x0d8001a8|32|UNKNOWN|Unknown}} | + | {{rld|0x0d8001a8|32|UNKNOWN}} |
− | {{rld|0x0d8001b0|32|HW_PLLSYS|}} | + | {{rld|0x0d8001b0|32|HW_PLLSYS}} |
− | {{rld|0x0d8001b4|32|HW_PLLSYSEXT|}} | + | {{rld|0x0d8001b4|32|HW_PLLSYSEXT}} |
− | {{rld|0x0d8001b8|32|HW_PLLDSK|}} | + | {{rld|0x0d8001b8|32|HW_PLLDSK}} |
− | {{rld|0x0d8001bc|32|HW_PLLDDR|}} | + | {{rld|0x0d8001bc|32|HW_PLLDDR}} |
− | {{rld|0x0d8001c0|32|HW_PLLDDREXT|}} | + | {{rld|0x0d8001c0|32|HW_PLLDDREXT}} |
− | {{rld|0x0d8001c4|32|HW_PLLVI|}} | + | {{rld|0x0d8001c4|32|HW_PLLVI}} |
− | {{rld|0x0d8001c8|32|HW_PLLVIEXT|}} | + | {{rld|0x0d8001c8|32|HW_PLLVIEXT}} |
− | {{rld|0x0d8001cc|32|HW_PLLAI|}} | + | {{rld|0x0d8001cc|32|HW_PLLAI}} |
− | {{rld|0x0d8001d0|32|HW_PLLAIEXT|}} | + | {{rld|0x0d8001d0|32|HW_PLLAIEXT}} |
− | {{rld|0x0d8001d4|32|HW_PLLUSB|}} | + | {{rld|0x0d8001d4|32|HW_PLLUSB}} |
− | {{rld|0x0d8001d8|32|HW_PLLUSBEXT|}} | + | {{rld|0x0d8001d8|32|HW_PLLUSBEXT}} |
| {{rld|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}} | | {{rld|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}} |
| {{rld|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}} | | {{rld|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}} |