Changes

== Register List ==

== Register List ==

{{reglist|XN Controller}}

{{reglist|XN Controller}}

{{rld|0x0d8b0800|32|AHMN_MEM0_CONFIG|AHMN configuration for MEM0 protection}}

{{rld|0x0d8b0800|32|AHMN_CFGMEM0|AHMN configuration for MEM0 protection}}

{{rld|0x0d8b0804|32|AHMN_MEM1_CONFIG|AHMN configuration for MEM1 protection}}

{{rld|0x0d8b0804|32|AHMN_CFGMEM1|AHMN configuration for MEM1 protection}}

{{rld|0x0d8b0808|32|AHMN_MEM2_CONFIG|AHMN configuration for MEM2 protection}}

{{rld|0x0d8b0808|32|AHMN_CFGMEM2|AHMN configuration for MEM2 protection}}

{{rld|0x0d8b080c|32|AHMN_RDBI_MASK|AHMN read buffer invalidate mask}}

{{rld|0x0d8b080c|32|AHMN_RDBIMSK|AHMN read buffer invalidate mask}}

{{rld|0x0d8b0820|32|AHMN_ERROR_MASK|AHMN protection violation's error mask}}

{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}

{{rld|0x0d8b0824|32|AHMN_ERROR|AHMN protection violation's error state}}

{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt state}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0850|32|AHMN_TRANSFER_STATE|AHMN read/write transfer state}}

{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN read/write transfer state}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}