Hardware/Espresso: Difference between revisions

No edit summary
Line 1: Line 1:
'''Espresso''' is the code name for the Wii U's PowerPC processor. Unlike the [https://wiibrew.org/wiki/Broadway Broadway], the Espresso contains a secure [[Espresso Boot ROM|boot ROM]] so that if the [[Hardware/Starbuck|Starbuck]] is taken over, Espresso code execution should not be possible.
'''Espresso''' is the code name for the Wii U's PowerPC processor. Unlike the [https://wiibrew.org/wiki/Broadway Broadway], the Espresso contains a secure [[Espresso Boot ROM|boot ROM]] so that if the [[Hardware/Starbuck|Starbuck]] is taken over, Espresso code execution should not be possible.


== Special Purpose Registers ==
== MSR ==
{| class="wikitable"
!|Bits
!|Description
|-
|0
|LE
|-
|1
|RI
|-
|2
|PM
|-
|3
|Reserved
|-
|4
|DR
|-
|5
|IR
|-
|6
|IP
|-
|7
|Reserved
|-
|8
|FE1
|-
|9
|BE
|-
|10
|SE
|-
|11
|FE0
|-
|12
|ME
|-
|13
|FP
|-
|14
|PR
|-
|15
|EE
|-
|16
|ILE
|-
|17
|Reserved
|-
|18
|POW
|-
|19-31
|Reserved
|}
 
== SPR ==
{| class="wikitable"
{| class="wikitable"
!|Index
!|Index
!|Name
!|Name
!|Description
|-
|-
|0x1
|0x1
|XER
|XER
|
|-
|-
|0x8
|0x8
|LR
|LR
|
|-
|-
|0x9
|0x9
|CTR
|CTR
|
|-
|-
|0x12
|0x12
|DSISR
|DSISR
|
|-
|-
|0x13
|0x13
|DAR
|DAR
|
|-
|-
|0x16
|0x16
|DEC
|DEC
|
|-
|-
|0x19
|0x19
|SDR1
|SDR1
|
|-
|-
|0x1A
|0x1A
|SRR0
|SRR0
|
|-
|-
|0x1B
|0x1B
|SRR1
|SRR1
|
|-
|-
|0x10C
|0x10C
|UTBL
|UTBL
|
|-
|-
|0x10D
|0x10D
|UTBU
|UTBU
|
|-
|-
|0x110
|0x110
|SPRG0
|SPRG0
|
|-
|-
|0x111
|0x111
|SPRG1
|SPRG1
|
|-
|-
|0x112
|0x112
|SPRG2
|SPRG2
|
|-
|-
|0x113
|0x113
|SPRG3
|SPRG3
|
|-
|-
|0x11A
|0x11A
|EAR
|EAR
|
|-
|-
|0x11C
|0x11C
|TBL
|TBL
|
|-
|-
|0x11D
|0x11D
|TBU
|TBU
|
|-
|-
|0x11F
|0x11F
|PVR
|PVR
|
|-
|-
|0x210
|0x210
|IBAT0U
|IBAT0U
|
|-
|-
|0x211
|0x211
|IBAT0L
|IBAT0L
|
|-
|-
|0x212
|0x212
|IBAT1U
|IBAT1U
|
|-
|-
|0x213
|0x213
|IBAT1L
|IBAT1L
|
|-
|-
|0x214
|0x214
|IBAT2U
|IBAT2U
|
|-
|-
|0x215
|0x215
|IBAT2L
|IBAT2L
|
|-
|-
|0x216
|0x216
|IBAT3U
|IBAT3U
|
|-
|-
|0x217
|0x217
|IBAT3L
|IBAT3L
|
|-
|-
|0x218
|0x218
|DBAT0U
|DBAT0U
|
|-
|-
|0x219
|0x219
|DBAT0L
|DBAT0L
|
|-
|-
|0x21A
|0x21A
|DBAT1U
|DBAT1U
|
|-
|-
|0x21B
|0x21B
|DBAT1L
|DBAT1L
|
|-
|-
|0x21C
|0x21C
|DBAT2U
|DBAT2U
|
|-
|-
|0x21D
|0x21D
|DBAT2L
|DBAT2L
|
|-
|-
|0x21E
|0x21E
|DBAT3U
|DBAT3U
|
|-
|-
|0x21F
|0x21F
|DBAT3L
|DBAT3L
|
|-
|-
|0x230
|0x230
|IBAT4U
|IBAT4U
|
|-
|-
|0x231
|0x231
|IBAT4L
|IBAT4L
|
|-
|-
|0x232
|0x232
|IBAT5U
|IBAT5U
|
|-
|-
|0x233
|0x233
|IBAT5L
|IBAT5L
|
|-
|-
|0x234
|0x234
|IBAT6U
|IBAT6U
|
|-
|-
|0x235
|0x235
|IBAT6L
|IBAT6L
|
|-
|-
|0x236
|0x236
|IBAT7U
|IBAT7U
|
|-
|-
|0x237
|0x237
|IBAT7L
|IBAT7L
|
|-
|-
|0x238
|0x238
|DBAT4U
|DBAT4U
|
|-
|-
|0x239
|0x239
|DBAT4L
|DBAT4L
|
|-
|-
|0x23A
|0x23A
|DBAT5U
|DBAT5U
|
|-
|-
|0x23B
|0x23B
|DBAT5L
|DBAT5L
|
|-
|-
|0x23C
|0x23C
|DBAT6U
|DBAT6U
|
|-
|-
|0x23D
|0x23D
|DBAT6L
|DBAT6L
|
|-
|-
|0x23E
|0x23E
|DBAT7U
|DBAT7U
|
|-
|-
|0x23F
|0x23F
|DBAT7L
|DBAT7L
|
|-
|-
|0x380
|0x380
|UGQR0
|UGQR0
|
|-
|-
|0x381
|0x381
|UGQR1
|UGQR1
|
|-
|-
|0x382
|0x382
|UGQR2
|UGQR2
|
|-
|-
|0x383
|0x383
|UGQR3
|UGQR3
|
|-
|-
|0x384
|0x384
|UGQR4
|UGQR4
|
|-
|-
|0x385
|0x385
|UGQR5
|UGQR5
|
|-
|-
|0x386
|0x386
|UGQR6
|UGQR6
|
|-
|-
|0x387
|0x387
|UGQR7
|UGQR7
|
|-
|-
|0x388
|0x388
|UHID2
|UHID2
|
|-
|-
|0x389
|0x389
|UWPAR
|UWPAR
|
|-
|-
|0x38A
|0x38A
|UDMAU
|UDMAU
|
|-
|-
|0x38B
|0x38B
|UDMAL
|UDMAL
|
|-
|-
|0x390
|0x390
|GQR0
|GQR0
|
|-
|-
|0x391
|0x391
|GQR1
|GQR1
|
|-
|-
|0x392
|0x392
|GQR2
|GQR2
|
|-
|-
|0x393
|0x393
|GQR3
|GQR3
|
|-
|-
|0x394
|0x394
|GQR4
|GQR4
|
|-
|-
|0x395
|0x395
|GQR5
|GQR5
|
|-
|-
|0x396
|0x396
|GQR6
|GQR6
|
|-
|-
|0x397
|0x397
|GQR7
|GQR7
|
|-
|-
|0x398
|0x398
|HID2
|[[#HID2|HID2]]
|
|-
|-
|0x399
|0x399
|WPAR
|WPAR
|
|-
|-
|0x39A
|0x39A
|DMA_U
|[[#DMAU|DMAU]]
|
|-
|-
|0x39B
|0x39B
|DMA_L
|[[#DMAL|DMAL]]
|
|-
|-
|0x3A8
|0x3A8
|UMMCR0
|UMMCR0
|
|-
|-
|0x3A9
|0x3A9
|UPMC1
|UPMC1
|
|-
|-
|0x3AA
|0x3AA
|UPMC2
|UPMC2
|
|-
|-
|0x3AB
|0x3AB
|USIA
|USIA
|
|-
|-
|0x3AC
|0x3AC
|UMMCR1
|UMMCR1
|
|-
|-
|0x3AD
|0x3AD
|UPMC3
|UPMC3
|
|-
|-
|0x3AE
|0x3AE
|UPMC4
|UPMC4
|
|-
|-
|0x3B0
|0x3B0
|[[#HID5|HID5]]
|[[#HID5|HID5]]
|
|-
|-
|0x3B2
|0x3B2
|PCSR
|PCSR
|
|-
|-
|0x3B3
|0x3B3
|[[#SCR|SCR]]
|[[#SCR|SCR]]
|
|-
|-
|0x3B4
|0x3B4
|CAR
|CAR
|
|-
|-
|0x3B5
|0x3B5
|BCR
|BCR
|
|-
|-
|0x3B6
|0x3B6
|WPSAR
|WPSAR
|
|-
|-
|0x3B8
|0x3B8
|MMCR0
|MMCR0
|
|-
|-
|0x3B9
|0x3B9
|PMC1
|PMC1
|
|-
|-
|0x3BA
|0x3BA
|PMC2
|PMC2
|
|-
|-
|0x3BB
|0x3BB
|SIA
|SIA
|
|-
|-
|0x3BC
|0x3BC
|MMCR1
|MMCR1
|
|-
|-
|0x3BD
|0x3BD
|PMC3
|PMC3
|
|-
|-
|0x3BE
|0x3BE
|PMC4
|PMC4
|
|-
|-
|0x3D0
|0x3D0
|DCATE
|DCATE
|
|-
|-
|0x3D1
|0x3D1
|DCATR
|DCATR
|
|-
|-
|0x3D8
|0x3D8
|DMATL0
|DMATL0
|
|-
|-
|0x3D9
|0x3D9
|DMATU0
|DMATU0
|
|-
|-
|0x3DA
|0x3DA
|DMATR0
|DMATR0
|
|-
|-
|0x3DB
|0x3DB
|DMATL1
|DMATL1
|
|-
|-
|0x3DC
|0x3DC
|DMATU1
|DMATU1
|
|-
|-
|0x3DD
|0x3DD
|DMATR1
|DMATR1
|
|-
|-
|0x3EF
|0x3EF
|UPIR
|PIR
|CPU core index (Processor Index Register)
|-
|-
|0x3F0
|0x3F0
|HID0
|[[#HID0|HID0]]
|
|-
|-
|0x3F1
|0x3F1
|HID1
|[[#HID1|HID1]]
|
|-
|-
|0x3F2
|0x3F2
|IABR
|IABR
|
|-
|-
|0x3F3
|0x3F3
|HID4
|[[#HID4|HID4]]
|
|-
|-
|0x3F4
|0x3F4
|TDCL
|TDCL
|
|-
|-
|0x3F5
|0x3F5
|DABR
|DABR
|
|-
|-
|0x3F9
|0x3F9
|L2CR
|[[#L2CR|L2CR]]
|
|-
|-
|0x3FA
|0x3FA
|TDCH
|TDCH
|
|-
|-
|0x3FB
|0x3FB
|ICTC
|ICTC
|
|-
|-
|0x3FC
|0x3FC
|THRM1
|THRM1
|
|-
|-
|0x3FD
|0x3FD
|THRM2
|THRM2
|
|-
|-
|0x3FE
|0x3FE
|THRM3
|THRM3
|
|}
 
=== DMAU ===
{| class="wikitable"
!|Bits
!|Description
|-
|-
|0x3FF
|0-4
|PIR
|DMA_LEN_U
|
|-
|5-31
|MEM_ADDR
|}
|}


=== HID5 ===
=== DMAL ===
{| class="wikitable"
{| class="wikitable"
!|Bit
!|Bits
!|Description
!|Description
|-
|-
|0
|0
|Enable HID5
|DMA_F
|-
|-
|1
|1
|Enable PIR
|DMA_T
|-
|2-3
|DMA_LEN_L
|-
|4
|DMA_LD
|-
|5-31
|LC_ADDR
|}
|}


=== SCR ===
=== L2CR ===
{| class="wikitable"
{| class="wikitable"
!|Bit
!|Bits
!|Description
!|Description
|-
|0
|L2IP
|-
|1-17
|Reserved
|-
|18
|L2TS
|-
|19
|L2WT
|-
|20
|Reserved
|-
|21
|L2I
|-
|22
|L2DO
|-
|23-29
|Reserved
|-
|30
|L2CE
|-
|-
|31
|31
|Set before exiting bootrom? If somehow set before then, uses a secret alternate set of ancast keys and prod ECC?
|L2E
|}
 
=== HID0 ===
{| class="wikitable"
!|Bits
!|Description
|-
|0
|NOOPTI
|-
|1
|Reserved
|-
|2
|BHT
|-
|3
|ABE
|-
|4
|Reserved
|-
|5
|BTIC
|-
|6
|DCFA
|-
|7
|SGE
|-
|8
|IFEM
|-
|9
|SPD
|-
|10
|DCFI
|-
|11
|ICFI
|-
|12
|DLOCK
|-
|13
|ILOCK
|-
|14
|DCE
|-
|15
|ICE
|-
|16
|NHR
|-
|17-19
|Reserved
|-
|20
|DPM
|-
|21
|SLEEP
|-
|22
|NAP
|-
|23
|DOZE
|-
|24
|PAR
|-
|25
|ECLK
|-
|26
|Reserved
|-
|27
|BCLK
|-
|28
|EBD
|-
|29
|EBA
|-
|-
|30
|30
|Bootrom enabled (clear only)
|DBP
|-
|31
|EMCP
|}
 
=== HID1 ===
{| class="wikitable"
!|Bits
!|Description
|-
|0-26
|Reserved
|-
|27
|PC4
|-
|28
|PC3
|-
|-
|29
|29
|Keystore 00..1f enabled (clear only)
|PC2
|-
|30
|PC1
|-
|31
|PC0
|}
 
=== HID2 ===
{| class="wikitable"
!|Bits
!|Description
|-
|0-15
|Reserved
|-
|16
|DQOEE
|-
|17
|DCMEE
|-
|18
|DNCEE
|-
|19
|DCHEE
|-
|20
|DQOERR
|-
|21
|DCMERR
|-
|22
|DNCERR
|-
|23
|DCHERR
|-
|24-27
|DMAQL
|-
|-
|28
|28
|Keystore 20..3f enabled (clear only). Set just after reading provisioning u32?
|LCE
|-
|29
|PSE
|-
|30
|WPE
|-
|31
|LSQE
|}
 
=== HID4 ===
{| class="wikitable"
!|Bits
!|Description
|-
|0-19
|Reserved
|-
|20
|L2CFI
|-
|21
|L2MUM
|-
|22
|DBP
|-
|23
|LPE
|-
|24
|ST0
|-
|-
|27
|25
|If bit27 and bit26 are set, uses vWii ancast keys.
|SBE
|-
|-
|26
|26
|If bit26 and bit27 are set, uses vWii ancast keys.
|Reserved
|-
|27-28
|BPD
|-
|29-30
|L2FM
|-
|31
|Reserved
|}
 
=== HID5 ===
{| class="wikitable"
!|Bits
!|Description
|-
|0-28
|Reserved
|-
|29
|Enable PIR
|-
|31
|Enable HID5
|}
 
=== SCR ===
{| class="wikitable"
!|Bits
!|Description
|-
|0-17
|Reserved
|-
|18
|Core0 has a pending ICI
|-
|19
|Core1 has a pending ICI
|-
|20
|Core2 has a pending ICI
|-
|21
|Enable Core2
|-
|22
|Enable Core1
|-
|23-24
|Reserved
|-
|-
|25
|25
|If unset when booting from alternate ancast keys, errors and loops forever.
|If unset when booting from alternate ancast keys, errors and loops forever.
|-
|-
|24
|26
|?
|If bit26 and bit27 are set, uses vWii ancast keys.
|-
|-
|23
|27
|?
|If bit27 and bit26 are set, uses vWii ancast keys.
|-
|-
|22
|28
|EnableCore1
|Keystore 20..3f enabled (clear only). Set just after reading provisioning u32?
|-
|-
|21
|29
|EnableCore2
|Keystore 00..1f enabled (clear only)
|-
|-
|20
|30
|HasICICore2
|Bootrom enabled (clear only)
|-
|-
|19
|31
|HasICICore1
|Set before exiting bootrom? If somehow set before then, uses a secret alternate set of ancast keys and prod ECC?
|-
|18
|HasICICore0
|}
|}