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Hardware/Processor interface (view source)
Revision as of 03:11, 19 February 2024
, 03:11, 19 February 2024no edit summary
Line 78:
Line 78:
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−==Register List==
+== Register List ==
{{reglist|Processor Interface}}
{{reglist|Processor Interface}}
−{{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}}
+{{rla|0x0c000000|32|PI_PPCINTSTS|Triggered IRQs for the PPC core}}
−{{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}}
+{{rla|0x0c000004|32|PI_PPCINTEN|Allowed IRQs for the PPC core}}
−{{rla|0x0c000078|32|PI_INTSR_CPU0|Triggered IRQs for CPU0}}
+{{rla|0x0c000040|32||}}
−{{rla|0x0c00007c|32|PI_INTMR_CPU0|Allowed IRQs for CPU0}}
+{{rla|0x0c000044|32||}}
−{{rla|0x0c000080|32|PI_INTSR_CPU1|Triggered IRQs for CPU1}}
+{{rla|0x0c000048|32||}}
−{{rla|0x0c000084|32|PI_INTMR_CPU1|Allowed IRQs for CPU1}}
+{{rla|0x0c00004c|32||}}
−{{rla|0x0c000088|32|PI_INTSR_CPU2|Triggered IRQs for CPU2}}
+{{rla|0x0c000050|32||}}
−{{rla|0x0c00008c|32|PI_INTMR_CPU2|Allowed IRQs for CPU2}}
+{{rla|0x0c000054|32||}}
+{{rla|0x0c000058|32||}}
+{{rla|0x0c00005c|32||}}
+{{rla|0x0c000060|32||}}
+{{rla|0x0c000064|32||}}
+{{rla|0x0c000068|32||}}
+{{rla|0x0c00006c|32||}}
+{{rla|0x0c000078|32|PI_PPC0INTSTS|Triggered IRQs for PPC core 0}}
+{{rla|0x0c00007c|32|PI_PPC0INTEN|Allowed IRQs for PPC core 0}}
+{{rla|0x0c000080|32|PI_PPC1INTSTS|Triggered IRQs for PPC core 1}}
+{{rla|0x0c000084|32|PI_PPC1INTEN|Allowed IRQs for PPC core 1}}
+{{rla|0x0c000088|32|PI_PPC2INTSTS|Triggered IRQs for PPC core 2}}
+{{rla|0x0c00008c|32|PI_PPC2INTEN|Allowed IRQs for PPC core 2}}
|}
|}
−==Register Details==
+== Register Details ==