Hardware/DRH: Difference between revisions

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Add pinout
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The DRH contains an ARM926EJ-S CPU which runs the <code>LVC_</code> part of the firmware blob.
The DRH contains an ARM926EJ-S CPU which runs the <code>LVC_</code> part of the firmware blob.
=== Pinout ===
This pinout is for the DRH-WUP '''only'''. The DRH-WUP-1 has a different pinout due to running off another voltage (1v1).
{| class="wikitable"
|-
|'''14''' || x || x || Crystal || Crystal || 5GHz D4 || 5GHz D5 || 5GHz D6 || 1v25 || GND || FLASH MOSI || FLASH MISO || FLASH CLK || 3v3 || to TP140
|-
|'''13''' || 3v3 || 3v3 || 3v3 || to TP190 || || 5GHz D2 || || 1v25 || GND || || FLASH CS || 3v3 || 3v3 || to TP179
|-
|'''12''' || GND (behind FIL39) || 3v3 || 3v3 || || 5GHz D1 || || 5GHz D3 || 1v25 || || FLASH WP || || 3v3 || || FLASH RESET
|-
|'''11''' || 1v25 (behind FIL37) || GND || GND || GND || || GND || GND || 1v25 || to TP90/5GHz Pin 19 || || to TP82, R678, then SoC || 3v3 || x || GND
|-
|'''10''' || 3v3 (behind FIL42) || 3v3 (behind FIL42) || GND || GND || GND || 1v25 || 1v25 || 1v25 || GND || 1v25 || || 3v3 || || 3v3
|-
|'''9''' || Pulldown to FIL43 GND? || 3v3 (behind FIL42) || GND || || 1v25 || 1v25 || 1v25 || || GND || 1v25 || 3v3 || 3v3 || x || 3v3
|-
|'''8''' || GND (behind FIL43) || GND (behind FIL43) || GND || GND || 1v25 || 1v25 || 3v3 || 3v3 || 3v3 || 3v3 || 3v3 || to TP104 || || GND
|-
|'''7''' || 3v3 || 3v3 || GND || GND || 1v25 || 1v25 || 3v3 || 3v3 || 3v3 || || GND || || to TP108 || to TP106
|-
|'''6''' || USB D-(?)|| 3v3 || GND || GND || 1v25 || || 3v3 || 3v3 || || GND || GND || 1v25 || || x
|-
|'''5''' || USB D+(?)|| GND || GND || || 1v25 || 1v25 || 1v25 || 1v25 || 1v25 || GND || to SoC || || 1v25 || 1v25
|-
|'''4''' || GND || GND || || to SoC || 1v25 || || to SoC || to SoC || || GND || || 1v25 || || to SoC (pulled up to 1v25)
|-
|'''3''' || GND || GND || to SoC || || 1v25 || GND || GND || || GND || GND || to SoC || || 1v25 || 1v25
|-
|'''2''' || 3v3 || || GND || to SoC || 1v25 || GND || || to SoC || || to SoC || || to SoC || 1v25 || to TP192
|-
|'''1''' || GND || GND || to SoC || to SoC || 1v25 || GND || to SoC || to SoC || to SoC || to SoC || 1v25 || to SoC || 1v25 || to TP178
|-
| || '''A''' || '''B''' || '''C''' || '''D''' || '''E''' || '''F''' || '''G''' || '''H''' || '''I''' || '''J''' || '''K''' || '''L''' || '''M''' || '''N'''
|}

Revision as of 07:08, 23 April 2025

Top view of the DRH.
View of the DRH removed.

The DRH handles communication with up to two GamePads. It is similar to the DRC internally and communicates with IOSU through USB.

The DRH contains an ARM926EJ-S CPU which runs the LVC_ part of the firmware blob.

Pinout

This pinout is for the DRH-WUP only. The DRH-WUP-1 has a different pinout due to running off another voltage (1v1).

14 x x Crystal Crystal 5GHz D4 5GHz D5 5GHz D6 1v25 GND FLASH MOSI FLASH MISO FLASH CLK 3v3 to TP140
13 3v3 3v3 3v3 to TP190 5GHz D2 1v25 GND FLASH CS 3v3 3v3 to TP179
12 GND (behind FIL39) 3v3 3v3 5GHz D1 5GHz D3 1v25 FLASH WP 3v3 FLASH RESET
11 1v25 (behind FIL37) GND GND GND GND GND 1v25 to TP90/5GHz Pin 19 to TP82, R678, then SoC 3v3 x GND
10 3v3 (behind FIL42) 3v3 (behind FIL42) GND GND GND 1v25 1v25 1v25 GND 1v25 3v3 3v3
9 Pulldown to FIL43 GND? 3v3 (behind FIL42) GND 1v25 1v25 1v25 GND 1v25 3v3 3v3 x 3v3
8 GND (behind FIL43) GND (behind FIL43) GND GND 1v25 1v25 3v3 3v3 3v3 3v3 3v3 to TP104 GND
7 3v3 3v3 GND GND 1v25 1v25 3v3 3v3 3v3 GND to TP108 to TP106
6 USB D-(?) 3v3 GND GND 1v25 3v3 3v3 GND GND 1v25 x
5 USB D+(?) GND GND 1v25 1v25 1v25 1v25 1v25 GND to SoC 1v25 1v25
4 GND GND to SoC 1v25 to SoC to SoC GND 1v25 to SoC (pulled up to 1v25)
3 GND GND to SoC 1v25 GND GND GND GND to SoC 1v25 1v25
2 3v3 GND to SoC 1v25 GND to SoC to SoC to SoC 1v25 to TP192
1 GND GND to SoC to SoC 1v25 GND to SoC to SoC to SoC to SoC 1v25 to SoC 1v25 to TP178
A B C D E F G H I J K L M N
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