Hardware/Latte IRQs
| Latte IRQs | |
| Access | |
|---|---|
| Espresso | Partial |
| Starbuck | Full |
| Registers | |
| Base | 0x0d800030, 0x0d800440 |
| Length | 0x14, 0x48 |
| Access size | 32 bits |
| Byte order | Big Endian |
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both. IOSU distinguishes interrupt sources that also existed in the Hollywood chipset (AHBALL) and new sources that are exclusive to the Latte (AHBLT). Additionally, the (emulated) Hollywood IRQ registers are still available for compat mode (vWii) and debugging.
IRQ Sources
| IRQ | Type | Description |
|---|---|---|
| (1 << 0) | AHBALL | Timer (Starbuck) |
| (1 << 1) | AHBALL | NAND Interface |
| (1 << 2) | AHBALL | AES Engine |
| (1 << 3) | AHBALL | SHA-1 Engine |
| (1 << 4) | AHBALL | USB Host Controller (EHCI-0) |
| (1 << 5) | AHBALL | USB Host Controller (OHCI-0:0) |
| (1 << 6) | AHBALL | USB Host Controller (OHCI-0:1) |
| (1 << 7) | AHBALL | SD Host Controller |
| (1 << 8) | AHBALL | 802.11 Wireless |
| (1 << 9) | AHBALL | Undefined |
| (1 << 10) | AHBALL | Latte GPIOs (Espresso) |
| (1 << 11) | AHBALL | Latte GPIOs (Starbuck) |
| (1 << 12) | AHBALL | SYSPROT |
| (1 << 13) | AHBALL | Undefined |
| (1 << 14) | AHBALL | Undefined |
| (1 << 15) | AHBALL | Undefined |
| (1 << 16) | AHBALL | USB Host Controller (EHCI-1) |
| (1 << 17) | AHBALL | Power button |
| (1 << 18) | AHBALL | Drive Interface |
| (1 << 19) | AHBALL | Undefined |
| (1 << 20) | AHBALL | EXI RTC |
| (1 << 21) | AHBALL | Undefined |
| (1 << 22) | AHBALL | Undefined |
| (1 << 23) | AHBALL | Undefined |
| (1 << 24) | AHBALL | Undefined |
| (1 << 25) | AHBALL | Undefined |
| (1 << 26) | AHBALL | Undefined |
| (1 << 27) | AHBALL | Undefined |
| (1 << 28) | AHBALL | SATA |
| (1 << 29) | AHBALL | Undefined |
| (1 << 30) | AHBALL | IPC (Espresso compat) |
| (1 << 31) | AHBALL | IPC (Starbuck compat) |
| (1 << 0) | AHBLT | SD Host Controller |
| (1 << 1) | AHBLT | Unknown |
| (1 << 2) | AHBLT | Unknown |
| (1 << 3) | AHBLT | Unknown |
| (1 << 4) | AHBLT | DRH |
| (1 << 5) | AHBLT | Unknown |
| (1 << 6) | AHBLT | Unknown |
| (1 << 7) | AHBLT | Unknown |
| (1 << 8) | AHBLT | AES Engine (AESS) |
| (1 << 9) | AHBLT | SHA-1 Engine (SHAS-1) |
| (1 << 10) | AHBLT | Unknown |
| (1 << 11) | AHBLT | Unknown |
| (1 << 12) | AHBLT | Unknown |
| (1 << 13) | AHBLT | I2C (Espresso) |
| (1 << 14) | AHBLT | I2C (Starbuck) |
| (1 << 15) | AHBLT | Undefined |
| (1 << 16) | AHBLT | Undefined |
| (1 << 17) | AHBLT | Undefined |
| (1 << 18) | AHBLT | Undefined |
| (1 << 19) | AHBLT | Undefined |
| (1 << 20) | AHBLT | Undefined |
| (1 << 21) | AHBLT | Undefined |
| (1 << 22) | AHBLT | Undefined |
| (1 << 23) | AHBLT | Undefined |
| (1 << 24) | AHBLT | Undefined |
| (1 << 25) | AHBLT | Undefined |
| (1 << 26) | AHBLT | IPC (Espresso CPU2) |
| (1 << 27) | AHBLT | IPC (Starbuck CPU2) |
| (1 << 28) | AHBLT | IPC (Espresso CPU1) |
| (1 << 29) | AHBLT | IPC (Starbuck CPU1) |
| (1 << 30) | AHBLT | IPC (Espresso CPU0) |
| (1 << 31) | AHBLT | IPC (Starbuck CPU0) |
Register List
Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for compat mode (vWii) and another for normal mode (Wii U). The subset used for normal mode is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core. There are also traces of additional unused registers which appear to have been used in the past for debugging purposes (ARM2x).
Compat block
| Global compat block | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800030 | 32 | LT_INTSR_PPC_COMPAT | Triggered IRQs for the PPC in vWii |
| 0x0d800034 | 32 | LT_INTMR_PPC_COMPAT | Allowed IRQs for the PPC in vWii |
| 0x0d800038 | 32 | LT_INTSR_ARM_COMPAT | Triggered IRQs for the ARM in vWii |
| 0x0d80003c | 32 | LT_INTMR_ARM_COMPAT | Allowed IRQs for the ARM in vWii |
| 0x0d800040 | 32 | LT_INTMR_ARM2x_COMPAT | Unknown |
SMP block
| SMP block - PPC core 0 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800440 | 32 | LT_INTSR_AHBALL_PPC0 | Triggered AHB IRQs for PPC core 0 (all) |
| 0x0d800444 | 32 | LT_INTSR_AHBLT_PPC0 | Triggered AHB IRQs for PPC core 0 (Latte only) |
| 0x0d800448 | 32 | LT_INTMR_AHBALL_PPC0 | Allowed AHB IRQs for PPC core 0 (all) |
| 0x0d80044c | 32 | LT_INTMR_AHBLT_PPC0 | Allowed AHB IRQs for PPC core 0 (Latte only) |
| SMP block - PPC core 1 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800450 | 32 | LT_INTSR_AHBALL_PPC1 | Triggered AHB IRQs for PPC core 1 (all) |
| 0x0d800454 | 32 | LT_INTSR_AHBLT_PPC1 | Triggered AHB IRQs for PPC core 1 (Latte only) |
| 0x0d800458 | 32 | LT_INTMR_AHBALL_PPC1 | Allowed AHB IRQs for PPC core 1 (all) |
| 0x0d80045c | 32 | LT_INTMR_AHBLT_PPC1 | Allowed AHB IRQs for PPC core 1 (Latte only) |
| SMP block - PPC core 2 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800460 | 32 | LT_INTSR_AHBALL_PPC2 | Triggered AHB IRQs for PPC core 2 (all) |
| 0x0d800464 | 32 | LT_INTSR_AHBLT_PPC2 | Triggered AHB IRQs for PPC core 2 (Latte only) |
| 0x0d800468 | 32 | LT_INTMR_AHBALL_PPC2 | Allowed AHB IRQs for PPC core 2 (all) |
| 0x0d80046c | 32 | LT_INTMR_AHBLT_PPC2 | Allowed AHB IRQs for PPC core 2 (Latte only) |
| SMP block - ARM core | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800470 | 32 | LT_INTSR_AHBALL_ARM | Triggered AHB IRQs for ARM core (all) |
| 0x0d800474 | 32 | LT_INTSR_AHBLT_ARM | Triggered AHB IRQs for ARM core (Latte only) |
| 0x0d800478 | 32 | LT_INTMR_AHBALL_ARM | Allowed AHB IRQs for ARM core (all) |
| 0x0d80047c | 32 | LT_INTMR_AHBLT_ARM | Allowed AHB IRQs for ARM core (Latte only) |
| 0x0d800480 | 32 | LT_INTMR_AHBALL_ARM2x | Unknown (all) |
| 0x0d800484 | 32 | LT_INTMR_AHBLT_ARM2x | Unknown (Latte only) |
Register descriptions
| LT_INTSR_AHBALL_PPCx (0x0d800440/0x0d800450/0x0d800460) | |
| 310 | |
| Access | R/Z |
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.
| LT_INTSR_AHBLT_PPCx (0x0d800444/0x0d800454/0x0d800464) | |
| 310 | |
| Access | R/Z |
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.
| LT_INTMR_AHBALL_PPCx (0x0d800448/0x0d800458/0x0d800468) | |
| 310 | |
| Access | R/W |
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.
| LT_INTMR_AHBLT_PPCx (0x0d80044c/0x0d80045c/0x0d80046c) | |
| 310 | |
| Access | R/W |
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.
| LT_INTSR_AHBALL_ARM (0x0d800470) | |
| 310 | |
| Access | R/Z |
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.
| LT_INTSR_AHBLT_ARM (0x0d800474) | |
| 310 | |
| Access | R/Z |
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.
| LT_INTMR_AHBALL_ARM (0x0d800478) | |
| 310 | |
| Access | R/W |
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
| LT_INTMR_AHBLT_ARM (0x0d80047c) | |
| 310 | |
| Access | R/W |
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.