Hardware/DSP

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DSP
Access
EspressoFull
StarbuckNone
Registers
Base0x0c280000
Length0x20000
Access size16 bits
Byte orderBig Endian
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The DSP is an extended version of the chip found on the Wii. Under CafeOS, it always runs the same microcode from ROM rather than being per-title [check]. It was extended to add an extra audio output for the GamePad, and to support the transition audio on OS loading screens. The MMIO address is different to where it is on the Wii.

At least two revisions of this chip are supported by CafeOS - Rev 0, present on Latte A2x and older (chiprev 0x10, 0x18 and 0x21); and Rev 1, present on Latte A3x and newer.

IRQ Sources

Bit Group Description
0 ALL Reserved
1 ALL Reserved
2 ALL Reserved
3 ALL DSP_AI2
4 ALL Reserved
5 ALL DSP_ACC
6 ALL Reserved
7 ALL DSP_DSP
8 ALL Reserved
9 ALL Reserved
10 ALL Reserved
11 ALL Reserved
12 LATTE DSP_AI
13 LATTE Reserved
14 LATTE Reserved
15 LATTE Reserved
16 LATTE Reserved
17 LATTE Reserved
18 LATTE Reserved
19 LATTE Reserved
20 LATTE Reserved
21 LATTE Reserved
22 LATTE Reserved
23 LATTE Reserved
24 LATTE Reserved
25 LATTE Reserved
26 LATTE Reserved
27 LATTE Reserved
28 LATTE Reserved
29 LATTE Reserved
30 LATTE Reserved
31 LATTE Reserved

Register List

Register Details

Most of these registers are exposed in snd_core.rpl as DSP* functions.

DSP_MAILBOX_IN_H (0x0c280000)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Set Data
Field Description
Set This must be set for the DSP to accept the data. It will be cleared when the data is received. (DSPCheckMailToDSP)
Data This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP. (DSPSendMailToDSP)

DSP_MAILBOX_IN_L (0x0c280002)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP. (DSPSendMailToDSP)

DSP_MAILBOX_OUT_H (0x0c280004)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R
Field Set Data
Field Description
Set This bit is set when a new message arrives from the DSP. (DSPCheckMailFromDSP)
Data This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP. (DSPReadMailFromDSP)

DSP_MAILBOX_OUT_L (0x0c280006)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP. (DSPReadMailFromDSP)


Control Register

This register holds states for all of the interfaces exposed by this register block.

DSP_CONTROL_STATUS (0x0c28000a)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W W W W W W R/W W R/W W R/W R/W R/W R/W
Field AIDINTMSK AIDINT BOOTMODE DMASTAT ARDMASTAT DMAINTMSK DSPINT ARINTMSK ARINT AI2DINTMSK AI2DINT HALT PIINT RES
Field Description
AIDINTMSK AI Interrupt Mask (Latte only)
AIDINT AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. (Latte only)
BOOTMODE When set, DSP will boot from IROM@0x8000. When clear, DSP will boot from IRAM@0x0000. (Set in DSPReset)
DMASTAT Set when a DSP-initiated DMA transfer is in progress
ARDMASTAT Set when an ARAM DMA transfer is in progress (DSPGetDMAStatus)
DSPINTMSK DSP Interrupt Mask
DSPINT DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
ACCINTMSK ACC Interrupt Mask
ACCINT ACC Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
AI2DINTMSK AI2 Interrupt Mask
AI2DINT AI2 Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
HALT Halt DSP - When set, the DSP will halt. When cleared, the DSP will resume. (DSPHalt/DSPUnhalt)
PIINT DSP Interrupt Assertion - Setting asserts the DSP Interrupt. (DSPAssertInt)
RES Writing 1 resets the DSP. (DSPReset)


Audio Interface 2 (GamePad)

This is the DMA from memory to the audio encoder. It can be seen as a circular buffer, although it can also behave as a "one-shot" buffer. During OS audio transitions, it is driven by the DSP, outside of this time can be driven directly by the CPU. In CafeOS snd_core, this encoder - despite being the legacy one from the Wii - is known as "AI2" and drives the GamePad audio output.

AI2_DMA_START_ADDR_H (0x0c280030)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field ADDR
Field Description
ADDR High halfword of DMA address to audio sample data.

AI2_DMA_START_ADDR_L (0x0c280032)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W U
Field ADDR
Field Description
ADDR Low halfword of DMA address to audio sample data.

AI2_DMA_START_ADDR_VH (0x0c280034)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field ADDR
Field Description
ADDR Top 3 bits of DMA address to audio sample data. Once written, DMA arena is locked chip-wide and cannot be changed without a hardware reset.[check] Only present on Rev 0 chips.

AI2_DMA_START_ADDR_UH (0x0c280050)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field ADDR
Field Description
BYTES Top 3 bits of DMA address to audio sample data. Freely modifiable, like the other DMA address registers. Only present on Rev 1 chips.

AI2_DMA_CONTROL_LENGTH (0x0c280036)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field CTRL LENGTH
Field Description
ENABLE If set, start playing the sample. If cleared, stop playing. (AI2GetDMAEnableFlag)
LENGTH Length of the sample divided by 32. The maximum value for this is 0x000FFFE0. (AI2GetDMALength)

AI2_DMA_BYTES_LEFT (0x0c28003a)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field BYTES
Field Description
BYTES Remaining byte count, divided by 32. (AI2GetDMABytesLeft)


Audio Interface (TV)

This DMA is for the new Latte-exclusive audio encoder, referred to as "AI" in snd_core and used for the TV output.

AI_DMA_START_ADDR_H (0x0c280040)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field ADDR
Field Description
ADDR High halfword of DMA address to audio sample data.

AI_DMA_START_ADDR_L (0x0c280042)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W U
Field ADDR
Field Description
ADDR Low halfword of DMA address to audio sample data.

The DMA address on Rev 0 chips is also influenced by #AI2_DMA_START_ADDR_VH.

AI_DMA_START_ADDR_UH (0x0c280054)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field ADDR
Field Description
BYTES Top 3 bits of DMA address to audio sample data. Freely modifiable, like the other DMA address registers. Only present on Rev 1 chips.

AI_DMA_CONTROL_LENGTH (0x0c280046)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field CTRL LENGTH
Field Description
ENABLE If set, start playing the sample. If cleared, stop playing. (AIGetDMAEnableFlag)
LENGTH Length of the sample divided by 32. The maximum value for this is 0x000FFFE0. (AIGetDMALength)

AI_DMA_BYTES_LEFT (0x0c28004a)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field BYTES
Field Description
BYTES Remaining byte count, divided by 32. (AIGetDMABytesLeft)


See also

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