|Access size||32 bits|
|Byte order||Big Endian|
The GX2 is the Wii U's main graphics processor, semantically a part of the Latte despite being used directly by the Espresso. The chip is a member of the Radeon R7xx family  (used in the Radeon HD 4330) clocked at 549.999775MHz.. While documentation perfectly matching the card is yet to be found, several documents can be brought together to form a reasonable picture of the register layout.
Reverse-engineering has revealed that the GX2's MMIO registers (referred to as GpuF0MMReg in AMD's docs) are at 0x0c200000; mapped at 0xfc200000 in Cafe OS userspace. The other MMIO locations (GpuF0Pcie, VGA_IO) are not known at this point.
- Register guide for a similar, but not identical, card. Covers 2D graphics, CRTCs, the memory controller, etc. Does not cover 3D. This reference has been successfully used to set up a framebuffer without Cafe OS running.
- 3D register guide. Applies to the whole R7xx family, so there should be no differences for the GX2.[check] Has not been tried on hardware at time of writing.
- Conceptual document explaining how to actually use the 3D engine, shader pipelines, caches, etc. Names registers, but does not give addresses (readers should cross-reference the 3D Register Reference Guide)
OSScreen is the easier of the two to reverse-engineer. It uses the registers at GpuF0MMReg:0x6100 to set up one framebuffer - which matches the D1GRPH registers according to the RV630 Register Reference Guide (see chapter 2.7.1 - Primary Display Graphics Control Registers) and uses the registers at GpuF0MMReg:0x6900 identically - which matches the D2GRPH registers according to the RS780 Register Reference Guide (see chapter 2.9.12 - Secondary Display Graphics Control Registers).
OSScreen uses the following D1 registers:
- D1CRTC_BLANK_CONTROL (sets D1CRTC_BLANK_DATA_EN)
- D1GRPH_CONTROL (sets D1GRPH_DEPTH to 32bpp, D1GRPH_FORMAT to ARGB 8888, and D1GRPH_ARRAY_MODE to ARRAY_LINEAR_ALIGNED)
- D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH (located at GpuF0MMReg:0x6914 with its D2 counterpart at GpuF0MMReg:0x6114 due to the R7xx D1 *_HIGH registers being located in the D2 block and vice versa)
- D1OVL_PITCH (for unknown reasons, the overlay is disabled)