Hardware/Latte I2C

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Latte I2C
Latte Registers
Base0x0d800000, 0x0d800570
Access size32 bits
Byte orderBig Endian
Latte13, 14
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This article is incomplete. Please help to improve it, or discuss the issue on the talk page.

(this article is a work-in-progress based on reverse-engineered code, the concepts presented here [buses, GPIO] have not been tested!)

The Latte includes dedicated hardware to communicate with the console's I²C devices, along with the GPIO-twiddling method used on the Wii.


Each pair of I²C lines available as Latte GPIOs appears to have an equivalent Latte controller.

Bus 1 (AV encoder)

This bus, using GPIO lines AV0I2CClock and AV0I2CData, are used to communicate with the Wii U's AV encoder, responsible for HDMI output. It's primarily accessed by tve.rpl from Cafe OS userspace. See AV Encoder.

Bus 2 (AV encoder #2)

This section or information is incomplete. Please help to improve it, or discuss the issue on the talk page.

The existence of this bus is implied by the AV1I2CClock and AV1I2CData GPIO lines, though what it's used for or where its Latte controller might be are currently unknown.

Bus 3 (SMC)

This bus is used by IOSU to communicate with the onboard SMC management chip, which handles miscellaneous functions like the power LED and ejecting the disc drive.


I²C Bus 1 Master Registers (AV encoder)
Address Bits Name Description
0x0d800068 32 HW_I2CIOPINTEN I2C interrupt enable
0x0d80006c 32 HW_I2CIOPINTSTS I2C interrupt status
0x0d800250 32 HW_I2CMCTRL I2C master control
0x0d800254 32 HW_I2CMDATAWR I2C master data write
0x0d800258 32 HW_I2CMWREN I2C master write enable
0x0d80025c 32 HW_I2CMDATARD I2C master data read

Despite being in the Wood address space, these registers do not appear to be present on the original Wii.[check]

I²C Bus 3 Master Registers (SMC)
Address Bits Name Description
0x0d800570 32 LT_I2CMCTRL I2C master control
0x0d800574 32 LT_I2CMDATAWR I2C master data write
0x0d800578 32 LT_I2CMWREN I2C master write enable
0x0d80057c 32 LT_I2CMDATARD I2C master data read
0x0d800580 32 LT_I2CIOPINTEN I2C interrupt enable
0x0d800584 32 LT_I2CIOPINTSTS I2C interrupt status