Hardware/Processor interface

Processor interface
Access
Espresso	Full
Starbuck	None
Registers
Base	0x0c000000
Length	0xc0000
Access size	32 bits
Byte order	Big Endian

IRQ Sources

Bit	Group	Description
0	ALL	ERROR
1	ALL	RSW
2	ALL	DI
3	ALL	SI
4	ALL	Reserved
5	ALL	AI
6	ALL	DSP
7	ALL	MEM
8	ALL	Reserved
9	ALL	Reserved
10	ALL	Reserved
11	ALL	Reserved
12	ALL	DEBUG
13	ALL	Reserved
14	ALL	Reserved
15	ALL	Reserved
16	LATTE	Reserved
17	LATTE	WG0_THRESHOLD
18	LATTE	WG1_THRESHOLD
19	LATTE	WG2_THRESHOLD
20	LATTE	MB_CPU0
21	LATTE	MB_CPU1
22	LATTE	MB_CPU2
23	LATTE	GPU7
24	LATTE	AHB
25	LATTE	Reserved
26	LATTE	Reserved
27	LATTE	Reserved
28	LATTE	Reserved
29	LATTE	Reserved
30	LATTE	Reserved
31	LATTE	Reserved

Register List

Processor Interface
Address	Bits	Name	Description
0x0c000000	32	PI_INTSTS	Triggered IRQs
0x0c000004	32	PI_INTEN	Allowed IRQs
0x0c000040	32	PI_WG0UNK0	Write Gather Pipe related
0x0c000044	32	PI_WG0UNK1	Write Gather Pipe related
0x0c000048	32	PI_WG0UNK2	Write Gather Pipe related
0x0c00004c	32	PI_WG0UNK3	Write Gather Pipe related
0x0c000050	32	PI_WG1UNK0	Write Gather Pipe related
0x0c000054	32	PI_WG1UNK1	Write Gather Pipe related
0x0c000058	32	PI_WG1UNK2	Write Gather Pipe related
0x0c00005c	32	PI_WG1UNK3	Write Gather Pipe related
0x0c000060	32	PI_WG2UNK0	Write Gather Pipe related
0x0c000064	32	PI_WG2UNK1	Write Gather Pipe related
0x0c000068	32	PI_WG2UNK2	Write Gather Pipe related
0x0c00006c	32	PI_WG2UNK3	Write Gather Pipe related
0x0c000078	32	PI_CPU0INTSTS	Triggered IRQs for CPU 0
0x0c00007c	32	PI_CPU0INTEN	Allowed IRQs for CPU 0
0x0c000080	32	PI_CPU1INTSTS	Triggered IRQs for CPU 1
0x0c000084	32	PI_CPU1INTEN	Allowed IRQs for CPU 1
0x0c000088	32	PI_CPU2INTSTS	Triggered IRQs for CPU 2
0x0c00008c	32	PI_CPU2INTEN	Allowed IRQs for CPU 2