Hardware/Processor interface

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Processor interface
Access
EspressoFull
StarbuckNone
Registers
Base0x0c000000
Length0xc0000
Access size32 bits
Byte orderBig Endian
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IRQ Sources

Bit Group Description
0 ALL ERROR
1 ALL RSW
2 ALL DI
3 ALL SI
4 ALL Reserved
5 ALL AI
6 ALL DSP
7 ALL MEM
8 WOOD VI
9 WOOD PE_TOKEN
10 WOOD PE_FINISH
11 WOOD CP
12 ALL DEBUG
13 ALL Reserved
14 WOOD AHB
15 ALL Reserved
16 LATTE Reserved
17 LATTE WG0_THRESHOLD
18 LATTE WG1_THRESHOLD
19 LATTE WG2_THRESHOLD
20 LATTE MB_CPU0
21 LATTE MB_CPU1
22 LATTE MB_CPU2
23 LATTE GPU7
24 LATTE AHB
25 LATTE Reserved
26 LATTE Reserved
27 LATTE Reserved
28 LATTE Reserved
29 LATTE Reserved
30 LATTE Reserved
31 LATTE Reserved

Register List

Processor Interface
Address Bits Name Description
0x0c000000 32 PI_INTSR Triggered IRQs
0x0c000004 32 PI_INTMSK Allowed IRQs
0x0c000024 32 PI_CONFIG Interface configuration
0x0c000040 32 PI_WG0UNK0 WG0 related
0x0c000044 32 PI_WG0UNK1 WG0 related
0x0c000048 32 PI_WG0UNK2 WG0 related
0x0c00004c 32 PI_WG0UNK3 WG0 related
0x0c000050 32 PI_WG1UNK0 WG1 related
0x0c000054 32 PI_WG1UNK1 WG1 related
0x0c000058 32 PI_WG1UNK2 WG1 related
0x0c00005c 32 PI_WG1UNK3 WG1 related
0x0c000060 32 PI_WG2UNK0 WG2 related
0x0c000064 32 PI_WG2UNK1 WG2 related
0x0c000068 32 PI_WG2UNK2 WG2 related
0x0c00006c 32 PI_WG2UNK3 WG2 related
0x0c000078 32 PI_INTSR0 Triggered IRQs for CPU 0
0x0c00007c 32 PI_INTMSK0 Allowed IRQs for CPU 0
0x0c000080 32 PI_INTSR1 Triggered IRQs for CPU 1
0x0c000084 32 PI_INTMSK1 Allowed IRQs for CPU 1
0x0c000088 32 PI_INTSR2 Triggered IRQs for CPU 2
0x0c00008c 32 PI_INTMSK2 Allowed IRQs for CPU 2
0x0c000090 32 PI_MBCPU0_CPU0 Unknown
0x0c000094 32 PI_MBCPU0_CPU1 Unknown
0x0c000098 32 PI_MBCPU0_CPU2 Unknown
0x0c00009c 32 PI_MBCPU_CPU0 Unknown
0x0c0000a0 32 PI_MBCPU_CPU1 Unknown
0x0c0000a4 32 PI_MBCPU_CPU2 Unknown

Register Details