Difference between revisions of "Hardware/Processor interface"
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Marionumber1 (talk | contribs) (→IRQ Sources: ACC and other DMA are the DSP ARAM and DSP DMA, respectively) |
Marionumber1 (talk | contribs) (→IRQ Sources: Add masks for IRQs) |
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| Line 12: | Line 12: | ||
! Description | ! Description | ||
! Connection | ! Connection | ||
| + | ! Mask | ||
|- | |- | ||
| − | |0 || Error || Processor Interface | + | |0 || Error || Processor Interface || 0x1 |
|- | |- | ||
| − | |1 || {{hw|DSP}} (all DSP IRQs) || Processor Interface | + | |1 || {{hw|DSP}} (all DSP IRQs) || Processor Interface || 0x40 |
|- | |- | ||
| − | |2 || {{hw|GX2}} || Processor Interface (Latte) | + | |2 || {{hw|GX2}} || Processor Interface (Latte) || 0x800000 |
|- | |- | ||
| − | |3 || GPIPPC (?) || AHB | + | |3 || GPIPPC (?) || AHB || 0x400 |
|- | |- | ||
| − | |4 || {{hw|I2C}} || AHB (Latte) | + | |4 || {{hw|I2C}} || AHB (Latte) || 0x2000 |
|- | |- | ||
| − | |5 || {{hw|Audio Interface}} (TV) || {{hw|DSP}} | + | |5 || {{hw|Audio Interface}} (TV) || {{hw|DSP}} || 0x8 |
|- | |- | ||
| − | |6 || {{hw|Audio Interface}} (Gamepad) || {{hw|DSP}} (Latte) | + | |6 || {{hw|Audio Interface}} (Gamepad) || {{hw|DSP}} (Latte) || 0x1000 |
|- | |- | ||
| − | |7 || DSP ARAM || {{hw|DSP}} | + | |7 || DSP ARAM || {{hw|DSP}} || 0x20 |
|- | |- | ||
| − | |8 || DSP DMA || {{hw|DSP}} | + | |8 || DSP DMA || {{hw|DSP}} || 0x80 |
|- | |- | ||
| − | |9 || {{hw|IPC}} (CPU0) || AHB (Latte) | + | |9 || {{hw|IPC}} (CPU0) || AHB (Latte) || 0x40000000 |
|- | |- | ||
| − | |10 || {{hw|IPC}} (CPU1) || AHB (Latte) | + | |10 || {{hw|IPC}} (CPU1) || AHB (Latte) || 0x10000000 |
|- | |- | ||
| − | |11 || {{hw|IPC}} (CPU2) || AHB (Latte) | + | |11 || {{hw|IPC}} (CPU2) || AHB (Latte) || 0x4000000 |
|- | |- | ||
| − | |12 || {{hw|Latte IRQs}} || Processor Interface (Latte) | + | |12 || {{hw|Latte IRQs}} || Processor Interface (Latte) || 0x1000000 |
|} | |} | ||
Revision as of 04:23, 21 August 2015
| Processor interface | |
| Access | |
|---|---|
| Espresso | Full |
| Starbuck | None |
| Registers | |
| Base | 0x0c000000 |
| Length | 0xc0000 |
| Access size | 32 bits |
| Byte order | Big Endian |
IRQ Sources
| IRQ | Description | Connection | Mask |
|---|---|---|---|
| 0 | Error | Processor Interface | 0x1 |
| 1 | DSP (all DSP IRQs) | Processor Interface | 0x40 |
| 2 | GX2 | Processor Interface (Latte) | 0x800000 |
| 3 | GPIPPC (?) | AHB | 0x400 |
| 4 | I2C | AHB (Latte) | 0x2000 |
| 5 | Audio Interface (TV) | DSP | 0x8 |
| 6 | Audio Interface (Gamepad) | DSP (Latte) | 0x1000 |
| 7 | DSP ARAM | DSP | 0x20 |
| 8 | DSP DMA | DSP | 0x80 |
| 9 | IPC (CPU0) | AHB (Latte) | 0x40000000 |
| 10 | IPC (CPU1) | AHB (Latte) | 0x10000000 |
| 11 | IPC (CPU2) | AHB (Latte) | 0x4000000 |
| 12 | Latte IRQs | Processor Interface (Latte) | 0x1000000 |
Register List
| Processor Interface | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0c000000 | 32 | PI_INTSR_GLOBAL | Globally-triggered IRQs |
| 0x0c000004 | 32 | PI_INTMR_GLOBAL | Globally-allowed IRQs |
| 0x0c000078 | 32 | PI_INTSR_CPU0 | Triggered IRQs for CPU0 |
| 0x0c00007c | 32 | PI_INTMR_CPU0 | Allowed IRQs for CPU0 |
| 0x0c000080 | 32 | PI_INTSR_CPU1 | Triggered IRQs for CPU1 |
| 0x0c000084 | 32 | PI_INTMR_CPU1 | Allowed IRQs for CPU1 |
| 0x0c000088 | 32 | PI_INTSR_CPU2 | Triggered IRQs for CPU2 |
| 0x0c00008c | 32 | PI_INTMR_CPU2 | Allowed IRQs for CPU2 |